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M16C/6K9 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Description
REJ03B0041-0100Z Rev.1.00 2003.06.06
The M16C/6K9 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 144-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. To communicate with host CPU, the LPC bus interface is built in. In this way, this MCU can work as slave controller in the personal computer system. The specification is target oriented specification for the development of M16C/6K9.
Features
* Memory capacity .................................... ROM (See Figure AA-4 ROM Expansion) RAM 3K to 5K bytes * The Min. time of instruction execution ... 62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V) * Supply voltage ....................................... 3.0 to 3.6V (f(XIN)=8MHZ with 0 wait) * Supply voltage for Program/Erase ......... 3.0 to 3.6V (CPU reprogram mode, f(XIN)=16MHZ with 1 wait) * Low power consumption ........................ 52.8mW ( f(XIN)=16MHZ, with 0 wait, VCC = 3.3V) * Interrupts ................................................ 38 internal and 16 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) * Key input interrupts .................................. 2 (8 inputs shared with1 interrupt request X 1; 8 inputs (with event latch) shared with1 interrupt request X 1) * Multifunction 16-bit timer ........................ 5 output timers + 6 input timers * Serial I/O ................................................ 5 channels (3 for UART or clock synchronous, 2 for clock synchronous) * DMAC .................................................... 2 channels * Host interface ......................................... LPC bus interface X 4 * A-D converter ......................................... 10 bits X 8 channels (Expandable up to 10 channels) * D-A converter ......................................... 8 bits X 2 channels * Comparator circuit ................................. 8 channels * PWM ...................................................... 8 bits X 6 channels * Watchdog timer ...................................... 1 * I2C bus interface .................................... 3 channels : M306K9FCLRP, 2 channels : M306K9F8LRP * PS/2 interface ........................................ 3 channels * Serial interrupt output ............................ 6 factors (2 fixed factors, 4 programmable factors) * Programmable I/O ................................. 129 _______ * Input port ................................................ 1 (P85 shared with NMI pin) * Clock generating circuit ......................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic)
Applications
Notebook PC, others
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this data sheet may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
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M16C/6K9 Group
Description
------Table of Contents-----Central Processing Unit (CPU) ..................... 14 Reset ............................................................. 17 Processor Mode ............................................ 27 Clock Generating Circuit ............................... 30 Protection ...................................................... 39 Interrupts ....................................................... 40 Watchdog Timer ............................................ 68 DMAC ........................................................... 70 Timer ............................................................. 79 Serial I/O ....................................................... 97 A-D Converter ............................................. 131 D-A Converter ............................................. 141 Comparator Circuit ...................................... 143 PWM Output Circuit .................................... 145 LPC Bus Interface ....................................... 149 Serial interrupt output .................................. 167 MULTI-MASTER I2C-BUS Interface ............ 178 PS2 Interface .............................................. 209 Programmable I/O Ports ............................. 224 Electrical Characteristics ............................. 246 Flash Memory Version ................................ 259
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The differences in M16C/6K group
M306K5F8LRP(In mass production) 144-pin 144-pin 144-pin 144-pin 3K bytes NEW DINOR Flash memory 64K bytes User ROM area Address 0F000016 - 0FFFFF16 Boot ROM area Address 0FF00016 - 0FFFFF16 5K bytes NEW DINOR Flash memory 128K bytes User ROM area Address 0E000016 - 0FFFFF16 Boot ROM area Address 0FF00016 - 0FFFFF16 3K bytes NEW DINOR Flash memory 68K bytes User ROM area Address 0EF00016 - 0FFFFF16 Boot ROM area Address 0FF00016 - 0FFFFF16 3K bytes NEW DINOR Flash memory 64K bytes User ROM area Address 0E800016 - 0F5FFF16 Address 0FE00016 - 0FFFFF16 Boot ROM area In parallel I/O mode Address 0FE0016 - 0FFFFF16 In CPU reprogram mode & standard serial I/O mode Address 0DE00016 - 0DFFFF16 Flash memory control register After reset XXXX00012 Flash memory recognition register After reset 000000002 Flash memory recognition register After reset XXXXXX102 Flash memory control register After reset 000000012 Vcc 3.0 - 3.6V FVCC 3.0 - 3.6V Not exist The input pin of power supply for program/erase 129 Port 0 - Port 16 3.3V Not Exist Exist 8-bit X 6 3 channels Flash memory control register After reset XX0000012 Vcc 3.0 - 3.6V Not exist Not exist 129 Port 0 - Port 16 3.3V Not Exist Exist 14-bit X 4 2 channels Flash memory control register After reset 000000002 Vcc 3.0 - 3.6V M2 pin 4.5 - 5.25V The input pin of power supply for program/erase Not exist 128 Port 0 - Port 16 without P84 3.3V/5V Exist Exist 14-bit X 4 2 channels M306K7F8LRP(In mass production) M306K9FCLRP(In mass production) M306K9F8LRP(Under development)
Rev.1.00
Flash memory recognition register After reset XXXXXX102 Flash memory control register After reset 000000012 Vcc 3.0 - 3.6V FVCC 3.0 - 3.6V Not exist The input pin of power supply for program/erase 129 Port 0 - Port 16 3.3V Not Exist Exist 8-bit X 6 2 channels 8 inputs shared with 1 interrupt request X 1 8 inputs (with event latch) shared with 1 interrupt request X 1 Detected only in the falling edge Can not be selected with 1 bit unit 8 inputs shared with 1 interrupt request X 1 8 inputs (with event latch) shared with 1 interrupt request X 1 Detected only in the falling edge Can not be selected with 1 bit unit 8 inputs shared with 1 interrupt request X 1 8 inputs (with event latch) shared with 1 interrupt request X 1 Detected in either of the edges by the dege selection Can be selected with 1 bit unit Exist Exist 8 inputs shared with 1 interrupt request X 1 8 inputs (with event latch) shared with 1 interrupt request X 1 Detected in either of the edges by the dege selection Can be selected with 1 bit unit Exist Not Exist
Type name
Pin numbers
M16C/6K9 Group
RAM
Jun 06, 2003
ROM
Built-in ROM area
Description
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Address 03B416
Address 03B716 After reset 000000002
The power supply for program/erase
M2 pin
FVCC pin
Programmable I/O
The I/O voltage in P2, P3 Programmable I/O ports
ISA bus interface
Serial interrupt output & LPC bus interface
PWM output circuit
I2C bus interface
Key input interrupt
Timer B TB2IN
Note 1 : Timer B TB2IN refers to the count source input and pulse period measurement in event count mode/pulse input in pulse width measurement mode.
M16C/6K9 Group
Description
Pin configuration
Fig. AA-1 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
P11/CLK01 P12/RXD01 P13/TXD01 P14/INT71/CTS11/RTS11/CTS01/CLKS11 P15/INT81/CLK11 P16/INT91/RXD11 P17/INT101/TXD11 P20/TXD21 P21/RXD21 P22/CLK21 P23/CTS21/RTS21 P24 P25 P26 P27 VSS P30/LAD0 VCC P127 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37 P130 P131 P132 P133 P134 P135 P136 P137 P40/ TA00OUT/OBF00/PWM41 P41/TA10OUT/PWM51
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
P10/CTS01/RTS01 P126 P125/INT111 P124/INT102 P123/INT92 P122/INT82 P121/INT72 P120/INT61 P07 P06 P05 P04 P03 P02 P01 P00 P117 P116 P115 P114 P113 P112 P111/F1OUT1 P110/F1OUT0 P107/AN7/INT110 P106/AN6/INT100 P105/AN5/INT90 P104/AN4/INT80 P103/AN3/INT70 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN40/INT60
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
81 80 79 78 77 76 75 74 73
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
M306K9FCLRP
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P42/TA20OUT/GATEA20 P43/OBF01/SERIRQ P44/PWM01/OBF1 P45/PWM11/OBF2/PRST P46/PWM21/OBF3/CLKRUN FVCC P47/PWM31 VSS P140/KI10 P141/KI11 P142/KI12 P143/KI13 P144/KI14 P145/KI15 P146/KI16 P147/KI17 P50/KI00 P51/KI01 P52/KI02 P53/KI03 P54/KI04 P55/KI05 P56/KI06 P57 /CLKOUT/KI07 P150/TA01OUT/CLK31 P151/TA11OUT/SIN31 P152/TA21OUT/SOUT31 P60/CTS00/RTS00/SDA0 P61/CLK00/SCL0 P62/RXD00/SDA1 P63/TXD00/SCL1 P64/CTS10/RTS10/CTS00/CLKS10 P65/CLK10 P66/RXD10/TA3OUT P67/TXD10/TA4OUT P70/TXD20/PS2A0
P96/ANEX1/SOUT40/PWM30 P95/ANEX0/CLK40/PWM20 P94/DA1/TB40IN/PWM10 P93/DA0/TB30IN/PWM00 P92/SOUT30/INT5 P91/SIN30/INT4 P90/CLK30/INT3 P161/TB41IN/PWM50 P160/TB31IN/PWM40 P157/SIN41 P156/SOUT41 P155/CLK41 P154 P153 M1 M0 P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/TB2IN P83/TB1IN P82/TB0IN P81/TA4IN P80/ICCK P77/TA3IN/SCL2 P76/SDA2 P75/TA2IN/INT2/PS2B2 P74/INT1/PS2B1 P73/CTS20/RTS20/TA1IN/INT0/PS2B0 P72/CLK20/PS2A2 P71/RXD20/TA0IN/TB5IN/PS2A1
Package: 144PFB-A
Fig. AA-1 Pin configuration (top view)
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M16C/6K9 Group
Description
Pin configuration
Fig. AA-2 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
P11/CLK01 P12/RXD01 P13/TXD01 P14/INT71/CTS11/RTS11/CTS01/CLKS11 P15/INT81/CLK11 P16/INT91/RXD11 P17/INT101/TXD11 P20/TXD21 P21/RXD21 P22/CLK21 P23/CTS21/RTS21 P24 P25 P26 P27 VSS P30/LAD0 VCC P127 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37 P130 P131 P132 P133 P134 P135 P136 P137 P40/ TA00OUT/OBF00/PWM41 P41/TA10OUT/PWM51
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
P10/CTS01/RTS01 P126 P125/INT111 P124/INT102 P123/INT92 P122/INT82 P121/INT72 P120/INT61 P07 P06 P05 P04 P03 P02 P01 P00 P117 P116 P115 P114 P113 P112 P111/F1OUT1 P110/F1OUT0 P107/AN7/INT110 P106/AN6/INT100 P105/AN5/INT90 P104/AN4/INT80 P103/AN3/INT70 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN40/INT60
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2345 678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
81 80 79 78 77 76 75 74 73
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
M306K9F8LRP
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P42/TA20OUT/GATEA20 P43/OBF01/SERIRQ P44/PWM01/OBF1 P45/PWM11/OBF2/PRST P46/PWM21/OBF3/CLKRUN FVCC P47/PWM31 VSS P140/KI10 P141/KI11 P142/KI12 P143/KI13 P144/KI14 P145/KI15 P146/KI16 P147/KI17 P50/KI00 P51/KI01 P52/KI02 P53/KI03 P54/KI04 P55/KI05 P56/KI06 P57 /CLKOUT/KI07 P150/TA01OUT/CLK31 P151/TA11OUT/SIN31 P152/TA21OUT/SOUT31 P60/CTS00/RTS00/SDA0 P61/CLK00/SCL0 P62/RXD00/SDA1 P63/TXD00/SCL1 P64/CTS10/RTS10/CTS00/CLKS10 P65/CLK10 P66/RXD10/TA3OUT P67/TXD10/TA4OUT P70/TXD20/PS2A0
P96/ANEX1/SOUT40/PWM30 P95/ANEX0/CLK40/PWM20 P94/DA1/TB40IN/PWM10 P93/DA0/TB30IN/PWM00 P92/SOUT30/INT5 P91/SIN30/INT4 P90/CLK30/INT3 P161/TB41IN/PWM50 P160/TB31IN/PWM40 P157/SIN41 P156/SOUT41 P155/CLK41 P154 P153 M1 M0 P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/TB2IN P83/TB1IN P82/TB0IN P81/TA4IN P80/ICCK P77/TA3IN P76 P75/TA2IN/INT2/PS2B2 P74/INT1/PS2B1 P73/CTS20/RTS20/TA1IN/INT0/PS2B0 P72/CLK20/PS2A2 P71/RXD20/TA0IN/TB5IN/PS2A1
Package: 144PFB-A
Fig. AA-2 Pin configuration (top view)
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M16C/6K9 Group
Description
Block Diagram
Fig.AA-3 is a block diagram of the M16C/6K9 (144-pin version) group.
8 8 8 8 8 8 8
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Internal peripheral function
Timer Timer TA0(16 bits) Timer TA1(16 bits) Timer TA2(16 bits) Timer TA3(16 bits) Timer TA4(16 bits) Timer TB0(16 bits) Timer TB1(16 bits) Timer TB2(16 bits) Timer TB3(16 bits) Timer TB4(16 bits) Timer TB5(16 bits) Watchdog timer (15 bits) DMAC (2 channels) D-A converter (8 bits x 2channels) PS2 interface (3 channels) Serial interrupt output (6 factors) A-D converter (10 bits x 8 channels Expandable up to 10 channels) UART/clock synchronous SI/O (8 bits x 3 channels) Comparator (8 channels)
Host interface (LPC bus interface x 4 channels)
System clock generator XIN-XOUT XCIN-XCOUT Clock synchronous SI/O (8 bits x 2channels)
2
8
Port P8
7
I C bus interface (Note 3) PWM output (8 bits x 6channels)
Port P85 Port P9
M16C/60 series 16-bit CPU core
Registers
R0H R0 R0H R0L R1H R1 L R1H R1L RL R2 R 2 R3 A 3 A0 A 0 A1 FB 1 FB SB
Memory
ROM (Note1) RAM (Note2)
8
Program counter
PC
Stack pointer
ISP USP
Port P10
8
Vector table
INTB
Flag register
FLG
Multiplier
Port P16
Port P15
Port P14
Port P13
Port P12
Port P11
2
8
8
8
8
8
Note1 : ROM size depends on MCU type. Note2 : RAM size depends on MCU type. Note3 : A number of channels depends on MCU type.
Fig.AA-3 Block diagram of M16C/6K9 (144-pin version) group
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M16C/6K9 Group
Description
Performance Outline
Table AA-1 is a performance outline of M16C/6K9 (144-pin version) group. Table AA-1 Performance outline of M16C/6K9 (144-pin version) group Item Performance Number of basic instructions 91 instructions The Min. time of instruction execution 62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V) Memory ROM (See the figure of ROM Expansion) capacity RAM 3K to 5K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 P11 to P16 8 bitsx5, 2 bitsx1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 SI/O3, SI/O4 A-D converter D-A converter DMAC Watchdog timer Interrupt Host interface Comparator circuit PWM I2C bus interface PS2 interface Serial interrupt output Clock generating circuit Program/erase supply voltage Power consumption I/O I/O withstand voltage characteristics Output current Device configuration Package (Clock synchronous) x 2 10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources) 15 bits x 1 (with prescaler) 38 internal and 16 external sources, 4 software sources, 7 levels 4 channels (LPC bus interface) 8 channels 8 bits x 6 3 channels : M306K9FCLRP, 2 channels : M306K9F8LRP 3 channels 6 factors (2 fixed factors, 4 programmable factors) 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic)
3.0 to 3.6V (CPU reprogram mode, f(XIN)=16MHz with 1 wait) 52.8mW (3.3V, f(XIN)=16MHz, with 0 wait) 3.3V 5mA CMOS high performance silicon gate 144-pin plastic mold QFP
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M16C/6K9 Group
Description
Renesas plans to release the following products in the M16C/6K9 (144-pin version) group: (1) Support for flash memory version (2) ROM capacity (3) Package 144PFB-A : Plastic molded QFP(flash memory version)
ROM Size (Byte) External ROM 256K 128K 96K 80K 64K 32K Mask ROM version Flash version
M306K9FCLRP
M306K9F8LRP
Fig.AA-4 ROM expansion
Table AA-2 Product list Type No. M306K9FCLRP ROM size RAM size 128K bytes 5K bytes Package type I2C bus Interface 144PFB-A 3 channels
From June 2003 up to now Remarks Flash memory (NEW DINOR) version Flash memory (NEW DINOR) version
M306K9F8LRP**
64K bytes
3K bytes
144PFB-A
2 channels
**: Under development
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M16C/6K9 Group
Description
Type No. M30 6K 9 M 8 XXX RP
Package type RP : 144PFB-A
ROM No.
ROM type 8 : 64Kbytes C : 128Kbytes
Memory type M : Mask ROM version F : Flash version
Shows RAM capacity, pin count, etc (The value itself has no specific maeaning)
M16C/6K Group
M16C Family
Fig.AA-5 Type No., memory size, and package
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M16C/6K9 Group
Pin Description
Pin Description Pin name Signal name I/O type Vcc, Vss Power supply input ____________ RESET Reset input Input XIN Clock input Input XOUT Clock output Output
Function Apply 3.0 to 3.6 V to VCC . Apply 0V to VSS A "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. Connect to VSS This pin is a power supply input for on-chip flash memory programming. During the normal operation, 0V to 3.6V can be applied. When programming on-chip flash memory, 3.0V to 3.6V should be applied. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. This port supports CMOS input level. And output type supports CMOS 3 state or N channel open drain selectable. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as external interrupt pins as selected by software. This is an 8-bit I/O port equivalent to P0. (Except that output type just supports CMOS 3 state only). P20-P27 are available for directly driving LED's.P20 to P24 also function as UART2 or SI/O pins as selected by software. This is an 8-bit I/O port equivalent to P0. (Except that output type just supports CMOS 3 state only). The port can be used for LPC bus interface I/O pins by software selection. This is an 8-bit I/O port equivalent to P0. (Except that output type just supports CMOS 3 state only). By software selecting, the port can also be used for LPC bus interface I/O pins, Timer A0 to A2 output pins PWM output pins or serial interrupt output I/O pins. P40 to P46 pins' level can be read regardless the setting of input port or output port. If P40 or P43 are used for output ports, the function that clears P40 or P43 to "0" after the read of output data buffer from host CPU is available. This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only). Key on wake interrupt 0 and comparator input function support. P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software.
M0,M1 FVCC
AVCC AVSS VREF P00 to P07
Chip mode Input setting Power supply input for flash memory programming Analog power supply input Analog power supply input Reference Input voltage input I/O port P0 Input/output
P10 to P17 P20 to P27
I/O port P1 I/O port P2
Input/output Input/output
P30 to P37
I/O port P3
Input/output
P40 to P47
I/O port P4
Input/output
P50 to P57
I/O port P5
Input/output
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M16C/6K9 Group
Pin Description
Pin Description Pin name P60 to P67 Signal name I/O port P6 I/O type Function
Input/output This is an 8-bit I/O port equivalent to P0. (Except that P60 to P63's output type is N channel open drain only; P64 to P67's output type is CMOS 3 state only; P60 to P63 no internal pull-up registor support.) By software selecting, this port can be used for I2C-BUS interface, UART0/UART1 input/ output pin, timerA3,A4 output pin. When P60 to P63 used as I2C-BUS interface SDA,SCL, the input level of these pins are CMOS/SMBUS selectable. Input/output This is an 8-bit I/O port equivalent to P0. (Except that P70 to P77 output type is N channel open drain only; no internal pull-up registor support.) By software selecting, this port can be used for external interrupt input pin, timerA0 to A3 and timer B5 input pin, PS2 interface input/output pin, I2C interface (M306K9FCLRP only) or UART2 input/output pin. P70 to P75 pins' level can be read regardless of the setting of input port or output port. Input/output Input/output Input/output Input P80 to P84, P86, and P87 are I/O ports with the same functions as P0. (Except that P86 to P87's output type is CMOS 3 state only; P80 to P84's output type is N channel open drain only; P85 is input port only; the P80 to P84 and P85 are no internal pull-up registor support.) By software selecting, this port can be used for timer A4, B0 to B2, I2C-BUS interface I/O pins. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that ______ ______ also functions for NMI. The NMI interrupt is generated when ______ the input at this pin changes from "H" to "L". The NMI function cannot be cancelled using software.
P70 to P77
I/O port P7
P80 to P84, P86, P87, P85
I/O port P8
I/O port P85
P90 to P97
I/O port P9
P100 to P107
I/O port P10
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, the port can be used for external interrupt, timer B3 to B4, A-D converter extended input pins, A-D trigger, SI/O3, SI/O4 I/O pins, PWM, D-A converter output pins. Input/output This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) If the ports are set to input mode, the pull-up resistor can be set in bit unit. By software selecting, the port can be used for A-D converter, external interrupt input pins.
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M16C/6K9 Group
Pin Description
Pin Description Pin name P110 to P117 Signal name I/O port P11 I/O type Function
Input/output This is an 8-bit I/O port equivalent to P0. By software selecting, P110, P111 also function as clock output pins, which the frequency is the same with XIN (XCIN). Input/output This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, this port can be used for external interrupt input pin. Input/output This is an 8-bit I/O port equivalent to P0. (Except that output type is N channel open drain only; no internal pull-up registor support.) Input/output This is an 8-bit I/O port equivalent to P0. The port can be used for key on wake-up interrupt 1 input pins. P140 to P143 are available for directly driving LED's. In input mode, the pull-up register can be set in one bit unit by software. Input/output This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, these ports can be used for timer A0 to A2's output or SI/O3 and SI/O4 I/O pins. Input/output This is an 2-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, this port can be used for timer B3 and B4 input or PWM output pin.
P120 to P127
I/O port P12
P130 to P137
I/O port P13
P140 to P147
I/O port P14
P150 to P157
I/O port P15
P160, P161
I/O port P16
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M16C/6K9 Group
Memory
Operation of Functional Blocks
The M16C/6K9 (144-pin version) group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/ logic operations. Also peripheral units such as timers, serial I/O, D-A converter, DMAC, A-D converter, host bus interface, comparator, PWM output , I2C BUS interface, PS2 interface and I/O ports are included. The following explains each unit.
Memory
Fig.CA-1 is the memory map. The address space extends up to 1M bytes from address 0000016 to FFFFF16. From FFFFF16 to the address decreasing direction ROM is allocated. For example, in the M306K9FCLRP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as _______ the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 to the address increasing direction RAM is allocated. For example, in the M306K9FCLRP, 5K bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Fig.CA-2 to CA-5 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
For details, see Fig.CA-2 to Fig.CA-4
0040016 Internal RAM area XXXXX16
Type No.
Address XXXXX16 Address YYYYY16
FFE0016 Special page vector table FFFDC16
Undefined instruction
M306K9FCLRP M306K9F8LRP
017FF16 00FFF16
E000016 F000016
Inhibited
Overflow BRK instruction Address match Single step
YYYYY16 Internal ROM area FFFFF16 FFFFF16
Watchdog timer DBC NMI Reset
Fig.CA-1 Memory map
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M16C/6K9 Group
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Fig.BA-1 Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
b19
b0
R1(Note)
H
L Data registers
PC
Program counter
b15
b0
b19
b0
R2(Note)
INTB
H
L
Interrupt table register
b0
b15
b0
b15
R3(Note)
USP
User stack pointer
b15
b0
b15
b0
A0(Note) Address registers
ISP
Interrupt stack pointer
b15 b0
b15
b0
A1(Note)
SB
Static base register
b15 b0
b15
b0
FB(Note)
Frame base register
FLG
Flag register
IPL
U
I OBS Z DC
Note: These registers consist of two register banks.
Fig.BA-1 Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be u2sed for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M16C/6K9 Group
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Fig.BA-2 shows the flag register (FLG). The following explains the function of each flag: * Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged.
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CPU
* Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt No. 0 to 31 is executed. * Bits 8 to 11: Reserved area * Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with the three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15
b0
IPL
U
I
OBSZDC
Flag register (FLG)
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level (CPU) Reserved area
Fig.BA-2 Flag register (FLG)
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Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details of software resets.) This section explains the hardware reset. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Fig.VB-1 shows the example reset circuit. Fig.VB-2 shows the reset sequence.
3.3V 3.0V VCC 0V 3.3V RESET 0.6V 0V Example when VCC = 3.3V
RESET
VCC
Fig.VB-1 Example reset circuit
XIN More than 20 cycles are needed
RESET
BCLK
24cycles
Internal clock Single chip mode Address
FFFFC16 FFFFE16
Content of reset vector
Fig.VB-2 Reset sequence
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Reset
____________
Table VB-1 shows the statuses of the other pins while the RESET pin level is "L". Fig.VB-3 and VB-4 show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table VB-1 Pin status when RESET pin level is "L"
Status Pin name
P0 P1 P2, P3, P40 to P43 P44 P45 to P47 P50 P51 P52 P53 P54 P55 P56 P57 P6, P7, P80 to P84, P86, P87, P9, P10 P11, P12, P13, P14 P15, P16 CNVSS = VSS (M0) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating)
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Reset
(1) Processor mode register 0 (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Address match interrupt enable register (6) Protect register (7) Watchdog timer control register (8) Address match interrupt register 0
(000416)***
0016 0
(25) A-D conversion interrupt control register (26) UART2 transmit interrupt control register (27) UART2 receive interrupt control register (28) UART0 transmit interrupt control register (29) UART0 receive interrupt control register (30) UART1 transmit interrupt control register (31) UART1 receive interrupt control register (32) Timer A0 interrupt control register (33) Timer A1 interrupt control register (34) Timer A2 interrupt control register (35) Timer A3 interrupt control register (36) Timer A4 interrupt control register (37) Timer B0 interrupt control register (38) Timer B1 interrupt control register (39) Timer B2 interrupt control register (40) INT0 interrupt control register (41) INT1 interrupt control register (42) INT2 interrupt control register (43) PS20 shift register (44) PS20 status register (45) PS20 control register (46) PS21 shift register (47) PS21 status register (48) PS21 control register (49) PS22 shift register (50) PS22 status register (51) PS22 control register (52) PS2 mode register
(004E16)*** (004F16)*** (005016)*** (005116)*** (005216)*** (005316)*** (005416)*** (005516)*** (005616)*** (005716)*** (005816)*** (005916)*** (005A16)*** (005B16)*** (005C16)*** (005D16)*** (005E16)*** (005F16)*** (02A016)*** (02A116)*** (02A216)*** (02A416)*** (02A516)*** (02A616)*** (02A816)*** (02A916)*** (02AA16)*** (02AC16)***
?000 ?000 ?000 ?000 00?000 ?000 00?000 ?000 00?000 ?000 ?000 ?000 00?000 00?000 00?000 00?000 00?000 00?000 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
(000516)*** 0 0 0 0 0
(000616)*** 0 1 0 0 1 0 0 0 (000716)*** 0 0 1 0 0 0 0 0 (000916)*** (000A16)*** 00 000
(000F16)*** 0 0 0 ? ? ? ? ? (001016)*** (001116)*** (001216)*** 0016 0016 0000 0016 0016 0000
(9) Address match interrupt register 1
(001416)*** (001516)*** (001616)***
(10) DMA0 control register (11) DMA1 control register (12) I2C interrupt control register (13) SCL2, SDA2 interrupt control register (14) Timer B5 interrupt control register (15) INT3 interrupt control register (16) INT9 interrupt control register (17) Timer B4 interrupt control register (18) Timer B3 interrupt control register (19) SI/O4 interrupt control register (20) SI/O3 interrupt control register (21) Bus collision detection interrupt control register (22) DMA0 interrupt control register (23) DMA1 interrupt control register (24) Key input interrupt control register 0
(002C16)*** 0 0 0 0 0 ? 0 0 (003C16)*** 0 0 0 0 0 ? 0 0 (004116)*** (004216)*** (004316)*** (004416)*** (004516)*** (004616)*** (004716)*** (004816)*** (004916)*** (004A16)*** (004B16)*** (004C16)*** (004D16)*** ?000 ?000 ?000 00?000 00?000 ?000 ?000 00?000 00?000 00?000 00?000 00?000 ?000
x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-3 Device's internal status after a reset is cleared (1)
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Reset
(53) Data bus buffer status register 0 (54) Data bus buffer status register 1 (55) Data bus buffer status register 2 (56) Data bus buffer status register 3 (57) Data bus buffer control register 0 (58) Data bus buffer control register 1 (59) GateA20 control register (60) Port P11 direction register (61) Port P12 direction register (62) Port P13 direction register (63) Port P14 direction register (64) Port P15 direction register (65) Port P16 direction register (66) Port function selection register 0 (67) Port function selection register 1 (68) Port P4 input register (69) Port P7 input register (70) Pull-up control register 3 (71) Pull-up control register 4 (72) Port control register 1 (73) Port control register 2 (74) PWM0 prescaler (75) PWM0 register (76) PWM1 prescaler (77) PWM1 register (78) PWM2 prescaler (79) PWM2 register (80) PWM3 prescaler (81) PWM3 register (82) PWM4 prescaler (83) PWM4 register (84) PWM5 prescaler (85) PWM5 register (86) PWM control register 0
(02C116)*** (02C316)*** (02C516)*** (02C716)*** (02C816)*** (02C916)*** (02CA16)*** (02E216)*** (02E316)*** (02E616)*** (02E716)*** (02EA16)*** (02EB16)*** (02F816)*** (02F916)*** (02FA16)*** 0 (02FB16)*** 0 0 (02FC16)*** (02FD16)*** (02FE16)*** (02FF16)*** (030016)*** (030116)*** (030216)*** (030316)*** (030416)*** (030516)*** (030616)*** (030716)*** (030816)*** (030916)*** (030A16)*** (030B16)*** (030C16)***
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00 0016 0016
(87) PWM control register 1 (88) I2C2 address register (89) I2C2 control register 0 (90) I2C2 clock control register
2 (91) I C2 start/stop condition control register 2C2 control register 1 (92) I
(030D16)*** (031216)*** (031316)*** (031416)*** (031516)*** (031616)*** (031716)***
0016 0016 0016 0016 1A16 3016 0016
(93) I2C2 control register 2 (94) I2C2 status register (95) I2C0 address register (96) I2C0 control register 0 (97) I2C0 clock control register
2 (98) I C0 start/stop condition control register (99) I2C0 control register 1
(031816)*** 0 0 1 0 0 0 0 (032216)*** (032316)*** (032416)*** (032516)*** (032616)*** (032716)*** 0016 0016 0016 1A16 3016 0016
(100) I2C0 control register 2 (101) I2C0 status register (102) I2C1 address register (103) I2C1 control register 0
(032816)*** 0 0 1 0 0 0 0 (033216)*** (033316)*** (033416)*** (033516)*** (033616)*** (033716)*** 0016 0016 0016 1A16 3016 0016
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
(104) I2C1 clock control register
2 (105) I C1 start/stop condition control register (106) I2C1 control register 1
(107) I2C1 control register 2 (108) I2C1 status register (109) TimerB3,4,5 count start flag (110) Interrupt factor selection register 1 (111) Interrupt factor selection register 2 (112) Interrupt factor selection register 3 (113) Interrupt factor selection register 4 (114) Interrupt factor selection register 5 (115) TimerB3 mode register (116) TimerB4 mode register (117) TimerB5 mode register (118) Interrupt factor selection register 0 (119) SI/O3 control register (120) SI/O4 control register
(033816)*** 0 0 1 0 0 0 0 (034016)*** 0 0 0 (035616)*** (035716)*** (035816)*** (035916)*** (035A16)*** (035B16)*** 0 0 ? (035C16)*** 0 0 ? (035D16)*** 0 0 ? (035F16)*** (036216)*** (036616)*** 0016 0016 0016 0016 0016 0000 0000 0000 0016 4016 4016
x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-4 Device's internal status after a reset is cleared (2)
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Reset
(121) UART2 special mode register (122) UART2 transmit/receive mode register (123) UART2 transmit/receive control register 0 (124) UART2 transmit/receive control register 1 (125) Count start flag (126) Clock prescaler reset flag (127) One-shot start flag (128) Trigger select flag (129) Up-down flag (130) Timer A0 mode register (131) Timer A1 mode register (132) Timer A2 mode register (133) Timer A3 mode register (134) Timer A4 mode register (135) Timer B0 mode register (136) Timer B1 mode register (137) Timer B2 mode register (138) UART0 transmit/receive mode register (139) UART0 transmit/receive control register 0 (140) UART0 transmit/receive control register 1 (141) UART1 transmit/receive mode register (142) UART1 transmit/receive control register 0 (143) UART1 transmit/receive control register 1 (144) UART transmit/receive control register 2 (145) Flash memory recognition register (Note1) (146) Flash memory control register (Note1) (147) DMA0 cause select register (148) DMA1 cause select register
(037716)*** (037816)***
0016 0016
(149) A-D control register 2 (150) A-D control register 0 (151) A-D control register 1 (152) D-A control register (153) Comparator control register (154) Port P0 direction register
(03D416)*** 0 0 0 1 0 0 0 0 (03D616)*** 0 0 0 0 0 ? ? ? (03D716)*** (03DC16)*** (03DE16)*** (03E216)*** (03E316)*** (03E616)*** (03E716)*** (03EA16)*** (03EB16)*** (03EE16)*** (03EF16)*** (03F216)*** 0 0 (03F316)*** (03F616)*** (03FC16)*** (03FD16)*** (03FE16)*** (03FF16)*** 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00000 0016 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016
(037C16)*** 0 0 0 0 1 0 0 0 (037D16)*** 0 0 0 0 0 0 1 0 (038016)*** (038116)*** 0 (038216)*** 0 0 (038316)*** (038416)*** (039616)*** (039716)*** (039816)*** (039916)*** (039A16)*** (039B16)*** 0 0 ? (039C16)*** 0 0 ? (039D16)*** 0 0 ? (03A016)*** 00000 0016 0016 0016 0016 0016 0016 0016 0000 0000 0000 0016 0016
(155) Port P1 direction register (156) Port P2 direction register (157) Port P3 direction register (158) Port P4 direction register (159) Port P5 direction register (160) Port P6 direction register (161) Port P7 direction register (162) Port P8 direction register (163) Port P9 direction register (164) Port P10 direction register (165) Pull-up control register 0 (166) Pull-up control register 1 (167) Pull-up control register 2 (168) Port control register 0 (169) Data registers (R0/R1/R2/R3) (170) Address registers (A0/A1) (171) Frame base register (FB) (172) Interrupt table register (INTB) (173) User stack pointer (USP) (174) Interrupt stack pointer (ISP) (175) Static base register (SB) (176) Flag register (FLG)
(03A416)*** 0 0 0 0 1 0 0 0 (03A516)*** 0 0 0 0 0 0 1 0 (03A816)*** 0016
(03AC16)*** 0 0 0 0 1 0 0 0 (03AD16)*** 0 0 0 0 0 0 1 0 (03B016)*** (03B416)*** (03B716)*** (03B816)*** (03BA16)*** 0000000 10 000001 0016 0016
x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (Note1) This register exists only in the flash memory version.
Fig.VB-5 Device's internal status after a reset is cleared (3)
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Reset
(177) Serial interrupt control register 0 (178) Serial interrupt control register 1 (179) IRQ request register 0 (180) IRQ request register 1 (181) IRQ request register 2 (182) IRQ request register 3 (183) IRQ request register 4 (184) Serial interrupt control register 2 (185) LPC1 address register L (186) LPC1 address register H (187) LPC2 address register L (188) LPC2 address register H (189) LPC3 address register L (190) LPC3 address register H (191) LPC control register (192) Port function selection register 2 (193) Pull-up resistor control register 5 (194) Pull-up resistor control register 6 (195) Key input interrupt 1 enable register (196) Key input interrupt 1 edge selection register (197) P14 event register (198) Port control register 3
(02B016)*** (02B116)*** (02B216)*** (02B316)*** (02B416)*** (02B516)*** (02B616)*** (02B716)*** (02D016)*** (02D116)*** (02D216)*** (02D316)*** (02D416)*** (02D516)*** (02D616)*** (02F116)*** (02F216)*** (02F316)*** (02F416)*** (02F516)*** (02F616)*** (02F716)***
0016 0016 0016 0016 0016 0016 0016 1016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-6 Device's internal status after a reset is cleared (4)
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SFR
SFR
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 005F16 005D16 005A16 005416 005216 005116 005016 004B16 004C16 004816 004016 004116 004216
I2C2 interrupt control register (IIC2IC)
SCL2,SDA2 interrupt control register (SCLDA2IC)
Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR)
004316 004416 004516 004616
DMA0 interrupt control register (DM0IC) Timer B5 interrupt control register (TB5IC) LRESET interrupt control register (LRSTIC) INT3 interrupt control register (INT3IC) INT9 interrupt control register (INT9IC) Timer B4 interrupt control register (TB4IC)
UART1 receive interrupt control register (S1RIC)
004716
SI/O4 interrupt control register (S4IC) Timer B3 interrupt control register (TB3IC)
UART1 transmit interrupt control register (S1TIC)
Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0)
004916 004A16
SI/O4 interrupt control register (S4IC) INT6 interrupt control register (INT6IC) SI/O3 interrupt control register (S3IC) INT5 interrupt control register (INT5IC)
Bus collision detection interrupt control register (BCNIC)
Address match interrupt register 1 (RMAD1)
004D16 004E16 004F16
INT4 interrupt control register (INT4IC) INT8 interrupt control register (INT8IC) DMA1 interrupt control register (DM1IC) INT7 interrupt control register (INT7IC) Key input interrupt 0 control register (KUP0IC) A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC)
IBF0 interrupt control register (IBF0IC)
UART2 receive interrupt control register (S2RIC)
IBF1 interrupt control register (IBF1IC)
UART0 transmit interrupt control register (S0TIC)
I2C0 interrupt control register (IIC0IC)
UART0 receive interrupt control register (S0RIC)
SCL0,SDA0 interrupt control register (SCLDA0IC)
DMA0 source pointer (SAR0)
INT11 interrupt control register (INT11IC)
005316
UART1 transmit interrupt control register (S1TIC)
I2C1 interrupt control register (IIC1IC)
UART1 receive interrupt control register (S1RIC)
SCL1,SDA1 interrupt control register (SCLDA1IC)
DMA0 destination pointer (DAR0)
005516 005616 005716 005816
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
005916
INT10 interrupt control register (INT10IC) Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) INT7 interrupt control register (INT7IC) SI/O3 interrupt control register (S3IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) IBF2 interrupt control register (IBF2IC) Timer A4 interrupt control register (TA4IC) IBF3 interrupt control register (IBF3IC) Timer B0 interrupt control register (TB0IC)
SCL0,SDA0 interrupt control register (SCLDA0IC)
DMA1 source pointer (SAR1)
005B16
INT11 interrupt control register (INT11IC) Timer B1 interrupt control register (TB1IC)
SCL1,SDA1 interrupt control register (SCLDA1IC)
DMA1 destination pointer (DAR1)
005C16
DMA1 transfer counter (TCR1)
005E16
DMA1 control register (DM1CON)
006016 006116
INT10 interrupt control register (INT10IC) Timer B2 interrupt control register (TB2IC) Key input interrupt 1 control register (KUP1IC) INT0 interrupt control register (INT0IC) PS20 interrupt control register (PS20IC) INT1 interrupt control register (INT1IC) PS21 interrupt control register (PS21IC) INT2 interrupt control register (INT2IC) PS22 interrupt control register (PS22IC)
027D16 027E16 027F16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-2 Location of peripheral unit control registers (1)
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SFR
028016 028116 028216 028316 028416 028516 028616 028716 028816 028916 028A16 028B16 028C16 028D16 028E16 028F16 029016 029116 029216 029316 029416 029516 029616 029716 029816 029916 029A16 029B16 029C16 029D16 029E16 029F16 02A016 02A116 02A216 02A316 02A416 02A516 02A616 02A716 02A816 02A916 02AA16 02AB16 02AC16 02AD16 02AE16 02AF16 02B016 02B116 02B216 02B316 02B416 02B516 02B616 02B716 02B816 02B916 02BA16 02BB16 02BC16 02BD16 02BE16 02BF16
02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16
Data bus buffer register0 (DBB0) Data bus buffer status register0 (DBBSTS0) Data bus buffer register1 (DBB1) Data bus buffer status register1 (DBBSTS1) Data bus buffer register2 (DBB2) Data bus buffer status register2 (DBBSTS2) Data bus buffer register3 (DBB3) Data bus buffer status register3 (DBBSTS3) Data bus buffer control register0 (DBBCON0) Data bus buffer control register1 (DBBCON1) Gate A20 control register (GA20CON)
LPC1 address registerL (LPC1ADL) LPC1 address registerH (LPC1ADH) LPC2 address registerL (LPC2ADL) LPC2 address registerH (LPC2ADH) LPC3 address registerL (LPC3ADL) LPC3 address registerH (LPC3ADH) LPC control register (LPCCON)
PS20 shift register (PS20SR) PS20 status register (PS20STS) PS20 control register (PS20CON) PS21 shift register (PS21SR) PS21 status register (PS21STS) PS21 control register (PS21CON) PS22 shift register (PS22SR) PS22 status register (PS22STS) PS22 control register (PS22CON) PS2 mode register (PS2MOD)
02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16
Port P11 (P11) Port P12 (P12) Port P11 direction register (PD11) Port P12 direction register (PD12) Port P13 (P13) Port P14 (P14) Port P13 direction register (PD13) Port P14direction register (PD14) Port P15 (P15) Port P16 (P16) Port P15 direction register (PD15) Port P16 direction register (PD16)
Serial Interrupt control register 0 (SERCON0) Serial Interrupt control register 1 (SERCON1) IRQ request register 0 (IRQ0) IRQ request register 1 (IRQ1) IRQ request register 2 (IRQ2) IRQ request register 3 (IRQ3) IRQ request register 4 (IRQ4) Serial Interrupt control register 2 (SERCON2)
02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16
Port function selection register 2 (PSL2) Pull-up resistor control register 5 (PUR5) Pull-up resistor control register 6 (PUR6) Key input interrupt 1 enable register (KIN1EN)
Key input interrupt 1 edge selection regiter (KINSEL)
P14 event register (P14EV) Port control register3 (PCR3) Port function selection register0 (PSL0) Port function selection register1 (PSL1) Port P4 input register (P4PIN) Port P7 input register (P7PIN) Pull-up control register3 (PUR3) Pull-up control register4 (PUR4) Port control register1 (PCR1) Port control register2 (PCR2)
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-3 Location of peripheral unit control registers (2)
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SFR
030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16
PWM0 prescaler (PREPWM0) PWM0 register (PWM0) PWM1 prescaler (PREPWM1) PWM1 register (PWM1) PWM2 prescaler (PREPWM2) PWM2 register (PWM2) PWM3 prescaler (PREPWM3) PWM3 register (PWM3) PWM4 prescaler (PREPWM4) PWM4 register (PWM4) PWM5 prescaler (PREPWM5) PWM5 register (PWM5) PWM control register 0 (PWMCON0) PWM control register 1 (PWMCON1)
034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16
TimerB3,4,5 count start flag (TBSR)
I2C2 data shift register (S02) (Note2) I C2 address register (S0D2) (Note2) I2C2 control register 0 (S1D2) (Note2) I2C2 clock control register (S22) (Note2) I2C2 start/stop condition control register (S2D2) (Note2) I2C2 control register 1 (S3D2) (Note2) I2C2 control register 2 (S4D2) (Note2) I2C2 status register (S12) (Note2)
2
035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16
TimerB3 register (TB3) TimerB4 register (TB4) TimerB5 register (TB5) Interrupt event select register1 (IFSR1) Interrupt event select register2 (IFSR2) Interrupt event select register3 (IFSR3) Interrupt event select register4 (IFSR4) Interrupt event select register5 (IFSR5) TimerB3 mode register (TB3MR) TimerB4 mode register (TB4MR) TimerB5 mode register (TB5MR) Interrupt event select register0 (IFSR0) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 communication speed register (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 communication speed register (S4BRG)
I2C0 data shift register (S00) I2C0 address register (S0D0) I2C0 control register0 (S1D0) I2C0 clock control register (S20) I2C0 start/stop condition control register (S2D0) I2C0 control register1 (S3D0) I2C0 control register2 (S4D0) I2C0 status register (S10)
036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16
I2C1 data shift register (S01) I2C1 address register (S0D1) I2C1 control register0 (S1D1) I2C1 clock control register (S21) I2C1 start/stop condition control register (S2D1) I2C1 control register1 (S3D1) I2C1 control register2 (S4D1) I2C1 status register (S11)
037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 communication speed register (U2BRG) UART2 tranmit buffer register (U2TB) UART2 transmit/receive control register0 (U2C0) UART2 transmit/receive control register1 (U2C1) UART2 receive buffer register (U2RB)
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited. Note 2: Nothing is allocated in M306K9F8LRP.
Fig.CA-4 Location of peripheral unit control registers (3)
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SFR
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) TimerA0 (TA0) TimerA1 (TA1) TimerA2 (TA2) TimerA3 (TA3) TimerA4 (TA4) TimerB0 (TB0) TimerB1 (TB1) TimerB2 (TB2) TimerA0 mode register (TA0MR) TimerA1 mode register (TA1MR) TimerA2 mode register (TA2MR) TimerA3 mode register (TA3MR) TimerA4 mode register (TA4MR) TimerB0 mode register (TB0MR) TimerB1 mode register (TB1MR) TimerB2 mode register (TB2MR)
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16
A-D register0 (AD0) A-D register1 (AD1) A-D register2 (AD2) A-D register3 (AD3) A-D register4 (AD4) A-D register5 (AD5) A-D register6 (AD6) A-D register7 (AD7)
A-D control register2 (ADCON2) A-D control register0 (ADCON0) A-D control register1 (ADCON1) D-A register0 (DA0) D-A register1 (DA1) D-A control register (DACON) Comparator control register (CMPCON) Comparator data register (CMPD) Port P0 (P0) Port P1 (P1) Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 (P2) Port P3 (P3) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P4 (P4) Port P5 (P5) Port P4 direction register (P4D) Port P5 direction register (P5D) Port P6 (P6) Port P7 (P7) Port P6 direction register (P6D) Port P7 direction register (P7D) Port P8 (P8) Port P9 (P9) Port P8 direction register (P8D) Port P9 direction register (P9D) Port P10 (P10) Port P10 direction register (P10D)
UART0 transmit/receive mode register (U0MR) UART0 communication speed register (U0BRG) UART0 tranmit buffer register (U0TB) UART0 transmit/receive control register0 (U0C0) UART0 transmit/receive control register1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 communication speed register (U1BRG) UART1 tranmit buffer register (U1TB) UART1 transmit/receive control register0 (U1C0) UART1 transmit/receive control register1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register2 (UCON)
03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316
Flash memory recognition register (FMRR)
03F416 03F516 03F616
Flash memory control register (FMCR) DMA0 request cacse select register (DM0SL) DMA1 request cacse select register (DM1SL)
03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Pull-up control register0 (PUR0) Pull-up control register1 (PUR1) Pull-up control register2 (PUR2) Port control register0 (PCR0)
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-5 Location of peripheral unit control registers (4)
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M16C/6K9 Group
Software Reset
Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are retained.
Processor Mode (1) Types of Processor Mode
The single-chip mode is supported in processor mode. * Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. Ports P0 to P16 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. Fig. BG-1 shows the structure of processor mode register 0 and processor mode register 1.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
0
Symbol PM0
Address 000416
When reset 0016 (Note 2)
Bit symbol
PM00 PM01
Bit name
Processor mode bit
b1 b0
Function
0 0: Single-chip mode 0 1: Inhibited 1 0: Inhibited 1 1: Inhibited
RW
Reserved bit
PM03
Must always be set to "0"
The device is reset when this bit is set to "1". The value of this bit is "0" when read.
Software reset bit
Reserved bit
Must always be set to "0"
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
0
0
Symbol PM1
Address 000516
When reset 00000XX02
Bit symbol
Reserved bit
Bit name
Function
Must always be set to "0"
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Reserved bit PM17 Wait bit Must always be set to "0" 0 : No wait state 1 : Wait state inserted
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Fig.BG-1 Processor mode register 0 and 1
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Bus control
Bus control (1) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) . A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is executed in 2 BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Table.EF-1 shows the software wait and bus cycles. Fig.EF-1 shows example bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to "1".
Table.EF-1 Software waits and bus cycles
Area SFR Internal ROM/RAM Wait bit Invalid 0 1 Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles
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M16C/6K9 Group
Bus control
No wait
Bus cycle
(Note 1)
Bus cycle
(Note 1)
BCLK Write signal Read signal
Data bus Address bus Chip select
Output
Input
Address
Address
With wait
Bus cycle
(Note 1)
Bus cycle
(Note 1)
BCLK Write signal Read signal
Output Input
Data bus Address bus Chip select
Address
Address
Note 1: This timing sample shows the lenth of bus cycle. It is possible that the read cyles, write cycle comes after this cycle in succession.
Fig.EF-1 Typical bus timings using software wait
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M16C/6K9 Group
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table.WA-1 Main clock and sub clock generating circuits Use of clock Main clock generating circuit Sub clock generating circuit * CPU's operating clock source * CPU's operating clock source * Internal peripheral units' * Timer A/B's count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input
Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other
Example of oscillator circuit
Fig.WA-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure WA-2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Fig.WA-1 and WA-2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT (Note) Rd
XIN
XOUT Open
Externally derived clock CIN COUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Apply the feedback register between XIN and XOUT if required by oscillator maker.
Fig.WA-1 Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XCIN
XCOUT (Note) RCd
XCIN
XCOUT Open
Externally derived clock CCIN CCOUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Apply the feedback register between XCIN and XCOUT if required by oscillator maker.
Fig.WA-2 Examples of sub clock
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M16C/6K9 Group
Clock Generating Circuit
Clock Control
Fig.WA-3 shows the block diagram of the clock generating circuit.
XCIN CM04
XCOUT 1/32
fC32 f1 f1SIO2 fC fAD f8 f32 f8SIO2 f32SIO2
Sub clock CM10 "1" Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction Main clock CM02 CM05 XOUT b a c d Divider
CM07=0 BCLK fC CM07=1
SQ R
b a
1/2 1/2 1/2 1/2 1/2
c
CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16
d
Details of divider
Fig.WA-3 Clock generating circuit
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M16C/6K9 Group
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). After switching the CPU operation clock to sub clock stopping the clock reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit defaults to "1" when shifting from high speed mode or mid-speed mode to stop mode and after a reset.
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub clock oscillation has fully stabilized before switching. After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is either the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. When shifting from high speed mode or mid-speed mode to stop mode, the main clock division select bit (bit 6 at 000616) is set to "1". The bit maintains in low speed mode and low power save mode.
(4) Peripheral function clock
f1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It is used for the BCLK and for the watchdog timer. Fig.WA-4 shows the system clock control registers 0 and 1.
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M16C/6K9 Group
Clock Generating Circuit
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01
Address 000616 Bit name
Clock output function select bit
When reset 4816 Function
b1 b0
RW
0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output
0 :Do not stop peripheral clock in wait mode 1 :Stop peripheral clock in wait mode (Note8)
CM02 CM03 CM04 CM05
WAIT peripheral function clock stop bit XCIN-XCOUT drive capacity select bit (Note 2) Port XC select bit Main clock (XIN-XOUT) stop bit (Note 3) (Note 4) (Note 5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6)
0 : LOW 1 : HIGH 0 : I/O port 1 : XCIN-XCOUT generation 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT
CM06 CM07
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shiffing to stop mode. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with XIN, set this bit to "0". When main clock oscillation is operating by itself, set system clock select bit (CM07) to "1" before setting this bit to "1". Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains ON, so XIN turns pulled up to XOUT ("H") via the feedback resistor. Note 6: In the case of setting the bit from "0" to "1", set port XC select bit (CM04) to "1" and wait for the subclock being stable before wrting the bit. Don't write in the same time. In the case of setting the bit from "1" to "0", set main clock stop bit (CM05) to "0" and wait for the main clock being stable before write the bit. Note 7: The bit is set to "1" when shifting from high speed mode or mid speed mode to stop mode and after reset. The bit maintains in low speed mode and power save mode. Note 8: fc32 is not included. Do not set to "1" when using low-speed or low power dissipation mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit (Note4)
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Always set to "0" Always set to "0" Always set to "0" Always set to "0" 0 : LOW 1 : HIGH
b7 b6
RW
Reserved bit Reserved bit Reserved bit Reserved bit CM15 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
CM16 CM17
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shiffing to stop mode. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor turns null.
Fig.WA-4 System clock control registers 0 and 1
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M16C/6K9 Group
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed. By setting the f1 output function selection bits (bit0 and bit1 of address 02F116) ,f1 can be output via P110 and P111. By setting P110 output clock selection bit (bit7 of address 02F816), the clock output via P110 can be selected to f1 or fc.
Stop Mode
Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. The oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stop in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) ,SIO3,4 functions provided an external clock is selected. Table.WA-2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled.After the restoration by interrupt, the corresponding interrupt routine will be processed.When shifting from high speed mode or mid-speed mode to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to "1". Table.WA-2 Port status during stop mode Pin Port CLKOUT When fc selected When f8, f32 selected Single-chip mode Retains status before stop mode "H" Retains status before stop mode
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M16C/6K9 Group
Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, because the peripheral function clock (fc32) that is generated by sub clock does not stop, there is no reducing of power dissipation. Do not set the bit to "1" then enter wait mode in low speed mode and low power dissipation mode.Table.WA-3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table.WA-3 Port status during wait mode Pin Single-chip mode CLKOUT When fC selected Does not stop When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is maintained. Port maintained the status immediately prior to enterig wait mode
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M16C/6K9 Group
Status Transition Of BCLK
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table.WA-4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. After a reset, operation defaults to division by 8 mode. When shifting from high speed mode or mid-speed mode to stop mode, and after a reset main clock division select bit 0 (bit 6 at address 000616) is set to "1". It is matained in low speed mode and low power dissipation mode.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. After reset, it works in this mode. Note that oscillation of the main clock must have stabilized before transferring from this mode to No-division, Division by 2 and Division by 4 mode. Oscillation of the sub clock must have stabilized before transferring this mode to Lowspeed mode and Low power dissipation mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Precaution
In the case of switching the BCLK count source from XIN to XCIN, or from XCIN to XIN, it is necessary that the destination clock count source be stable. The transition should be waited by software after the oscillation being stable.
Table.WA-4 Operating modes dictated by settings of system clock control registers 0 and 1 CM17 0 1 Invalid 1 0 Invalid Invalid CM16 1 0 Invalid 1 0 Invalid Invalid CM07 0 0 0 0 0 1 1 CM06 0 0 1 0 0 Invalid Invalid CM05 0 0 0 0 0 0 1 CM04 Invalid Invalid Invalid Invalid Invalid 1 1 Operating mode of BCLK Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode
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M16C/6K9 Group
Power control
Power control
The following is a description of the power control modes:
Modes
Power control is available in three modes. (1) Normal operation mode * High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. * Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the sub clock. Each peripheral function operates according to its assigned clock. * Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the sub clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (2) Wait mode The CPU operation is stopped. The oscillators do not stop. (3) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Fig.WA-5 is the state transition diagram of (1) to (3).
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Power control
Transition of stop mode, wait mode
Reset
All oscillators stop
CM10 = "1"
WAIT command Medium-speed mode (Divided-by-8 mode) Interrupt WAIT command High-speed/mediumspeed mode Interrupt WAIT command low-speed/low power dissipation mode Interrupt
CPU operation stop
Stop mode
Interrupt Interrupt All oscillators stop
CM10 = "1"
Wait mode
CPU operation stop
Stop mode
All oscillators stop
Wait mode
CM10 = "1"
CPU operation stop
Stop mode
Interrupt
Wait mode
Normal mode
(Please see the diagram below on transition of normal mode)
Transition of normal mode
Main clock oscillation Sub clock stop Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" CM07 = "0" Note 1 CM06 = "1" CM04 = "0" Main clock is oscillating Sub clock is oscillating Low-speed mode
CM06 = "1"
Main clock is oscillating Sub clock is oscillating High-speed mode BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" Medium-speed mode (divided-by-4) BCLK : f(XIN)/4 CM07 = "0" CM17 = "1" CM06 = "0" CM16 = "0" Medium-speed mode (divided-by-2) BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-16) BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1"
CM07 = "0" Note1,Note3 Medium-speed mode (divided-by-8) BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" CM07 = "1" Note2
BCLK : f(XCIN) CM07 = "1"
CM05 = "0"
CM05 = "1"
CM04 = "0" Main clock is oscillating Sub clock is stop High-speed mode BCLK : f(XIN) CM07 = "0" CM17 = "0" CM06 = "0" Note1,Note3 CM06 = "0" CM16 = "0"
CM04 = "1"
CM07 = "1" Note 2 CM05 = "1" CM07 = "0" Note 1 CM06 = "0" Note 3 CM04 = "1"
Main clock is stop Sub clock is oscillating
Low power dissipation mode BCLK : f(XCIN) CM07 = "1"
Medium-speed mode (divided-by-2) BCLK : f(XIN)/2 CM07 = "0" CM17 = "0" CM06 = "0" CM16 = "1"
Medium-speed mode (divided-by-4) BCLK: f(XIN)/4 CM07 = "0" CM17 = "1" CM06 = "0" CM16 = "0"
Medium-speed mode (divided-by-16) BCLK : f(XIN)/16 CM07 = "0" CM17 = "1" CM06 = "0" CM16 = "1"
Note 1: Note 2: Note 3: Note 4:
Please switch after the main clock oscillation being stable. Please switch after the sub clock oscillation being stable. Please change the CM06 after CM16,CM17 being changed. Please transit following the arrow direction.
Fig.WA-5 State transition diagram of Power control mode
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Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Fig.WA-6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) can only be changed when the respective bit in the protect register is set to "1".
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
When reset XXXXX0002 Function RW
Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode registers 0 and 1 (addresses 000416 0 : Write-inhibited 1 : Write-enabled and 000516) Must be "0"
PRC1
Reserved bit
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Fig.WA-6 Protect register
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Interrupt
Interrupt Type of Interrupts
Fig.DD-1 lists the types of interrupts.
Software
Interrupt
Special
Hardware
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Fig.DD-1 Classification of interrupts * Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
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Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched
_______

M16C/6K9 Group
Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to "1". The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK interrupt A BRK interrupt occurs when executing the BRK instruction. * INT interrupt An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
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Hardware Interrupts
Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. * Reset ____________ Reset occurs if an "L" is input to the RESET pin. _______ * NMI interrupt _______ _______ An NMI interrupt occurs if an "L" is input to the NMI pin. ________ * DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. * Watchdog timer interrupt Generated by the watchdog timer. * Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed. * Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors are also dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. 1)Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. 2)DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. 3)Key-input interrupt 0
___
A key-input interrupt occurs if an "L" is input to the KI pin. 4) Key-input interrupt 1 ___ A key-input interrupt occurs if an "L" or "H" is input to the KI pin. 5)A-D conversion interrupt This is an interrupt that the A-D converter generates. 6)UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. 7)UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. 8)Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates 9)Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates.
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Interrupt
________
__________
10)INT0 interrupt through INT11 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to the INT pin. 11)IBF0 to IBF3 interrupt These are interrupts that host bus interface generates. ______________ 12) LRESET interrupt ______________ ______________ LRESET interrupt occurs if an "L" is input to LRESET pin. 13)I2C0,I2C1,I2C2,SCL0,SDA0,SCL1,SDA1,SCL2, SDA2 interrupt These are interrupts that I2C bus interface generates. 14)PS20 to PS22 interrupt These are interrupt that PS2 interface generates.
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Interrupt
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Fig.DD-2 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.
MSB
LSB Low address Mid address 0000 High address 0000
Vector address + 0 Vector address + 1 Vector address + 2
0000
Fig.DD-2 Format for specifying interrupt vector addresses * Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table.DD-1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table.DD-1 Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use
Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only.
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* Variable vector tables The addresses in the variable vector table can be modified, according to the user's settings. The start address of vector table is set to the interrupt table register (INTB). The 256-byte area subsequent that the start address is indicated by the INTB becomes the area for the variable vector tables. One vector table comprises 4 bytes. Set the first address of the interrupt routine in each vector table. Table.DD-2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
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Table.DD-2 Interrupts assigned to the variable vector tables and addresses of vector
Software interrupt number Software interrupt number 0 Software interrupt number 1 Software interrupt number 2 Software interrupt number 3 Software interrupt number 4 Software interrupt number 5 Software interrupt number 6 Software interrupt number 7 Software interrupt number 8 Software interrupt number 9 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63 Vector table address
Address (L) to address (H)
Interrupt source BRK instruction I2 C2
Remarks Cannot be masked by I flag
+0 to +3 (Note 1) +4 to +7 (Note 1) +8 to +11 (Note 1) +12 to +15 (Note 1) +16 to +19 (Note 1) +20 to +23 (Note 1) +24 to +27 (Note 1) +28 to +31 (Note 1) +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1) +44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to +63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) to +252 to +255 (Note 1)
SCL2, SDA2/DMA0 (Note 2) Timer B5/LRESET INT3 INT9
Timer B4/UART1 reception/SIO4 (Note 3) Timer B3/UART1 transmission (Note 3)
(Note 2)
SIO4/INT6 SIO3/INT5
(Note 3) (Note 3)
Bus collision detection/INT4 (Note 2) INT8 DMA1/INT7 (Note 3)
Key input interrupt 0 A-D UART2 transmit/IBF0 (Note 2) UART2 receive/IBF1 (Note 2) UART0 transmit/I2C0 (Note 2)
UART0 receive/SCL0,SDA0/INT11 (Note 3)
UART1 transmit/I2C1 (Note 3)
UART1 receive/SCL1,SDA1/INT10 (Note 3)
Timer A0 Timer A1/INT7/SIO3 (Note 3) Timer A2 Timer A3/IBF2 Timer A4/IBF3 (Note 2) (Note 2)
Timer B0/INT11/SCL0,SDA0 (Note 3) Timer B1/INT10/SCL1,SDA1 (Note 3) Timer B2/Key input interrupt 1 (Note 2) INT0/PS20 (Note 2) INT1/PS21 (Note 2) INT2/PS22 (Note 2) Cannot be masked by I flag
Software interrupt
Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause bit. Note 3: Depend on interrupt event selection bit setting. Please do not set same interrupt event at the same time.
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Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bits and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bits are located in the interrupt control register of each interrupt. The interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Fig.DD-3 and DD-4 shows the memory map of the interrupt control registers. The interrupt factors in the same vector share the same interrupt control register. Which factor to be used depends on interrupt factor selection bit of interrupt event selection register i(address:035F16,035616, to 035816, i = 0 to 3) setting. After setting the interrupt factor, the corresponding interrupt request bit must be set to "0" before changing the interrupt.
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol IIC2IC SCLDA2IC/DM0IC TB5IC/LRSTIC TB4IC/S1RIC/S4IC TB3IC/S1TIC KUP0IC ADIC S2TIC/IBF0IC S2RIC/IBF1IC SiTIC/IICjIC(i=0,1) (j=0,1) TAiIC(i=0,2) TAiIC/IBFjIC(i=3,4) (j=2,3) TB2IC/KUP1IC
Address 004116 004216 004316 004616 004716 004D16 004E16 004F16 005016 005116,005316 005116,005316 005516,005716 005816,005916 005816,005916 005C16
When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note 1)
Nothing is assigned.
Note 1: Can only be writing by "0" (Please do not write "1" to this bit)
Fig.DD-3 Interrupt control registers(1)
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Interrupt
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol Address INTiIC(i=3,9,8) 004416,004516,004B16 SiIC/INTjIC(i=4,3) 004816,004916 (j=6,5) 004816,004916 BCNIC/INT4IC 004A16 DM1IC/INT7IC 004C16 SiRIC/SCLDAjIC/INTkIC(i=0,1) 005216,005416 (j=0,1) 005216,005416 (k=11,10) 005216,005416 TA1IC/INT7IC/S3IC 005616 TBiIC/INTjIC/SCLDAkIC(i=0,1) 005A16,005B16 (j=11,10) 005A16,005B16 (k=0,1) 005A16,005B16 INTiIC/PS2jIC(i=0 to 2) 005D16 to 005F16 (j=0 to 2) 005D16 to 005F16
When reset XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002 XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to "0"
R
W
ILVL1
ILVL2
IR
Interrupt request bit
(Note 1)
POL
Polarity select bit
Reserved bit Nothing is assigned.
Note 1: Can only be written by "0" (Please do not write "1" to this bit)
Fig.DD-4 Interrupt control registers (2)
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Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bits and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bits in the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table.DD-3 shows the settings of interrupt priority levels and Table.DD-4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted: * interrupt enable flag (I flag) = 1 * interrupt request bit = 1 * interrupt priority level > processor interrupt priority level (IPL) The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bits, and the IPL are independent, and they are not affected each other.
Table.DD-3 Settings of interrupt priority levels
Interrupt priority level select bit
b2 b1 b0
Table.DD-4 Interrupt levels enabled according to the contents of the IPL
IPL
IPL2 IPL1 IPL0
Interrupt priority level
Priority order
Enabled interrupt priority levels
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
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Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occurrence, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
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Interrupt
Interrupt Sequence
An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the procession of interrupt sequence the processor executes instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Fig.DD-5 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
Fig.DD-5 Interrupt response time
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Interrupt
Time (a) is dependent on the instruction under execution. 30 cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table.DD-5 Table.DD-5 Time required for executing the interrupt sequence
Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd
________
16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1)
8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
Fig.DD-6 Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table.DD-6 is set in the IPL. Table.DD-6 Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels
_______
Value set in the IPL 7 0 Not changed
Watchdog timer, NMI Reset Other
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Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Fig.DD-7 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address MSB Stack area LSB Address MSB Stack area LSB [SP] New stack pointer value
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs
m-4 m-3 m-2 m-1 m m+1
Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Fig.DD-7 State of stack before and after acceptance of interrupt request The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Fig.DD-8 shows the operation of the saving registers. Note: Stack pointer is indicated by U flag when software number 32 - 63 INT command is executed, otherwise is indicated by ISP.
(1) Stack pointer (SP) contains even number
Address Stack area Sequence in which order registers are saved
(2) Stack pointer (SP) contains odd number
Address Stack area Sequence in which order registers are saved
[SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3 (Odd)
Program counter (PCL) Program counter (PCM)
[SP] - 5 (Even) [SP] - 4 (Odd) (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. [SP] - 3 (Even) [SP] - 2 (Odd)
Program counter (PCL) Program counter (PCM) Flag register (FLGL) (FLGH)
Program counter (PCH)
(3) (4) (1) (2) Finished saving registers in four operations. Saved simultaneously, all 8 bits
[SP] - 2 (Even) Flag register (FLGL) [SP] - 1 (Odd) [SP] (Even)
Flag register Program (FLGH) counter (PCH)
[SP] - 1 (Even) Flag register [SP] (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Fig.DD-8 Operation of saving registers
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Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bits. If the same interrupt priority level is assigned, however, the interrupt with higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Fig.DD-9 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine
Interrupt priority level judgement circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Fig.DD-10 shows the circuit that judges the interrupt priority level..
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_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Fig.DD-9 Hardware interrupts priorities
Priority level of each interrupt INT1/PS21 Timer B2/Key input interrupt 1 Timer B0/INT11/SCL0,SDA0 Timer A3/IBF2 Timer A1/INT7/SIO3
UART1 reception/SCL1,SDA1/INT10 UART0 reception/SCL0,SDA0/INT11
Level 0 (initial value)
High
UART2 reception/ IBF1 INT2/PS22 INT0/PS20 Timer B1/INT10/SCL1,SDA1 Timer A4/IBF3 Timer A2 Timer A0 UART1 transmission/ I2C1 UART0 transmission/ I2C0 A-D conversion DMA1/INT7 Bus collision detection/INT4 SIO4/INT6 Timer B4/ UART1 reception/ SIO4 INT3 SCL2, SDA2/ DMA0 UART2 transmission/IBF0 Key input interrupt 0 INT8 SIO3/INT5 Timer B3/ UART1 transmission INT9 Timer B5/ LRESET I2C2 (Note 1)
Priority of peripheral I/O interrupts (if priority levels are same)
Low
Processor interrupt priority level (IPL)
To interrupt request level judgment output clock generation circuit (Fig. WA-3) Interrupt request accepted
Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Note 1: I2C exist in M306K9FCLRP
Fig.DD-10 Interrupt priority judgement circuit
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______
INT Interrupt Factor selection
Numbers of interrupt factors share the same interrupt registers in the addresses of 004516, 004816 - 004C16, 004F16 - 005616, 005816 -005F16. The setting of interrupt factor selection bits of interrupt factor selection registers 0 - 3 (addresses of 035F16, 035616 - 035816) select the interrupt factor. After the selection of interrupt factor, the corresponding interrupt request bit must be "0" before enabling the interrupt. Fig.DD-11 - Fig.DD-13 show the structure of interrupt factor selection register 0 - 3.
______
INT Interrupt
________ ________
INT0 to INT11 are triggered by the edges of external inputs. The edge polarity can be selected using the polarity select bit. _______ _______ _______ ________ INT0 to INT2 and INT4 to INT11 have polarity switching bit in the interrupt event select register. The polarity ______ switching bit has to set to "0" when INT interrupt event is not selected. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by
________
setting "1" in the INTi interrupt polarity switching bit of the interrupt factor selection register0,4 (035F16,035916). To select both edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0"). Fig.DD-11, Fig.DD-13 show the Interrupt factor selection register 0, 4.
Interrupt factor selection register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR0
Bit symbol
Address 035F16
When reset 0016
Bit name
INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit Interrupt factor selection bit (Selecting interrupt factor in the address of 004916) Interrupt factor selection bit (Selecting interrupt factor in the address of 004816)
Function
0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : SIO3 1 : INT5 0 : SIO4 1 : INT6 (Note 1)
RW
IFSR00 IFSR01 IFSR02 IFSR03 IFSR04 IFSR05 IFSR06
IFSR07
(Note 2)
Note 1: Do not select the bit if SIO3 is selected by interrupt factor selection register 3. Note 2: Do not select the bit if SIO4 is selected by interrupt factor selection register 5.
Fig.DD-11 Interrupt factor selection register(1)
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Interrupt factor selection register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol IFSR1
Address 035616
When reset 0016
Bit symbol
Reserved bit IFSR11
Bit name
Must be "0"
Function
RW
Interrupt factor selection bit (Selecting interrupt factor in the address of 004A16)
0 : Bus collision detection 1 : INT4 Must be "0"
Reserved bit IFSR13
Interrupt factor selection bit 0 : DMA1 (Selecting interrupt factor in the 1 : INT7 (Note 1) address of 004C16) Interrupt factor selection bit (Selecting interrupt factor in the address of 004F16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005016) Interrupt factor selection bit (Selecting interrupt factor in the address of 005116) Interrupt factor selection bit (Selecting interrupt factor in the address of 005316) 0 : UART2 transmission 1 : IBF0 0 : UART2 reception 1 : IBF1 0 : UART0 transmission 1 : I2C0 0 : UART1 transmission (Note 2) 1 : I2C1
IFSR14
IFSR15
IFSR16
IFSR17
Note 1: Do not select the bit if INT7 is selected by interrupt factor selection register 3. Note 2: Do not select the bit if UART1 transmission is selected by interrupt factor selection register 5.
Interrupt factor selection register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR2
Address 035716
When reset 0016
Bit symbol
IFSR20 IFSR21 IFSR22 IFSR23 IFSR24 IFSR25 IFSR26 IFSR27
Bit name
Interrupt factor selection bit (Selecting interrupt factor in the address of 005216)
b1 b0
Function
0 0 : UART0 reception 0 1 : SCL0,SDA0 (Note1) 1 0 : INT11 (Note1) 1 1 : Inhibited
b3 b2
RW
Interrupt factor selection bit (Selecting interrupt factor in the address of 005416)
0 0 : UART1 reception (Note 2) 0 1 : SCL1,SDA1 (Note1) 1 0 : INT10 (Note1) 1 1 : Inhibited
b5 b4
Interrupt factor selection bit (Selecting interrupt factor in the address of 005A16)
0 0 : Timer B0 0 1 : INT11 (Note1) 1 0 : SCL0,SDA0 (Note1) 1 1 : Inhibited
b7 b6
Interrupt factor selection bit (Selecting interrupt factor in the address of 005B16)
0 0 : Timer B1 0 1 : INT10 (Note1) 1 0 : SCL1,SDA1 (Note1) 1 1 : Inhibited
Note1 : Do not select INT10, INT11, SCL0, SDA0, SCL1, SDA1 simultaneously in the interrupt control registers. Note 2: Do not select the bit if UART1 reception is selected by interrupt factor selection register 5.
Fig.DD-12 Interrupt factor selection register(2)
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Interrupt factor selection register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR3
Address 035816
When reset 0016
Bit symbol
IFSR30 IFSR31 IFSR32 IFSR33 IFSR34 IFSR35 IFSR36 IFSR37
Bit name
Interrupt factor selection bits (Selecting interrupt factor in the address of 005616)
b1 b0
Function
0 0 : Timer A1 0 1 : INT7 (Note 1) 1 0 : SIO3 (Note 2) 1 1 : Inhibited 0 : Timer A3 1 : IBF2 0 : Timer A4 1 : IBF3 0 : Timer B2 1 : Key input interrupt 1 0 : INT0 1 : PS20 0 : INT1 1 : PS21 0 : INT2 1 : PS22
RW
Interrupt factor selection bit (Selecting interrupt factor in the address of 005816) Interrupt factor selection bit (Selecting interrupt factor in the address of 005916) Interrupt factor selection bit (Selecting interrupt factor in the address of 005C16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005D16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005E16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005F16)
Note 1: Do not select the bit if INT7 are selected by interrupt factor selection register 1. Note 2: Do not select the bit if SIO3 is selected by interrupt factor selection register 0.
Interrupt factor selection register 4
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol IFSR4
Address 035916
When reset 0016
Bit symbol
IFSR40 IFSR41 IFSR42 IFSR43 IFSR44 IFSR45
Bit name
INT6 Interrupt polarity switching bit INT7 Interrupt polarity switching bit INT8 Interrupt polarity switching bit INT9 Interrupt polarity switching bit INT10 Interrupt polarity switching bit INT11 Interrupt polarity switching bit
Function
0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges Must be "0"
RW
Reserved bits
Fig.DD-13 Interrupt factor selection register(3)
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Interrupt factor selection register 5
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol IFSR 5
Address 035A16
When reset 0016
Bit symbol
IFSR50
Bit name
Function
RW
Interrupt factor selection bit 0 : SCL2,SDA2 (Selecting interrupt factor in the 1 : DMA0 address of 004216) Interrupt factor selection bit 0 : Timer B5 (Selecting interrupt factor in the 1 : LRESET address of 004316)
b1 b0 Interrupt factor selection bit (Selecting interrupt factor in the 0 0 : Timer B4 0 1 : UART1 reception (Note 1) address of 004616) 1 0 : SIO4(Note 2) 1 1 : Inhibited
IFSR51
IFSR52
IFSR53
IFSR54
Interrupt factor selection bit 0 : Timer B3 (Selecting interrupt factor in the 1 : UART1 transmission (Note 3) address of 004716) Must be "0"
Reserved bits
Note 1. Do not select the bit if UART1 reception is selected by interrupt factor selection register 2. Note 2. Do not select the bit if SIO4 is selected by interrupt factor selection register 0. Note 3. Do not select the bit if UART1 transmission is selected by interrupt factor selection register 1.
Fig. DD-14 Interrupt factor selection register(4)
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________
NMI Interrupt
______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input.
Key Input Interrupt 0
If the direction register of any of P50 to P57 is set for input and a falling edge is input to that port, a key input interrupt 0 is generated. A key input interrupt 0 can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Fig.DD-14 shows the block diagram of the key input interrupt 0. Note that if an "L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt.
Pull-up transistor
Pull-up select bit Key input interrupt 0 control register Port P57 direction register Port P57 direction register (address 004D16)
P57/KI07 Pull-up transistor P56/KI06 Pull-up transistor Port P56 direction register Key input interrupt 0 request
Interrupt control circuit
Port P55 direction register
P55/KI05 Port P54 direction register
Pull-up transistor P54/KI04 Pull-up transistor P53/KI03 Pull-up transistor
Port P53 direction register
Port P52 direction register
P52/KI02 Port P51 direction register
Pull-up transistor P51/KI01
Pull-up transistor P50/KI00
Port P50 direction register
Fig.DD-15 Block diagram of key input interrupt 0
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Key Input Interrupt 1
If any of the bits of key input interrupt 1 enable register (Address: 02F416) are set to "1", the key input interrupt 1 request occurs when a falling or a rising edge is input to one of the corresponding pins. The effective input edge of key input interrupt 1 is determined by the edge selection bit of key input interrupt 1 edge selection register (Address: 02F516). When the bit is set to "0", at the falling edge, when the bit is set to "1", at the rising edge of the input signal to the corresponding pin, the interrupt request occurs respectively. When an effective rising edge or falling edge is input, "1" is set to the corresponding bit of P14 event register (Address: 02F616). By reading the register after the interrupt occurs, the pin, which the effective edge is input, can be confirmed even if the status of that pin has been changed. At the completion of the reading of P14 event register, the bits, whose value is "1" in reading, will be cleared automatically. A dummy write clears the register too. The registers, the block diagram and the timing of key input interrupt 1 are shown in Fig. DD-17, Fig. DD-18 and Fig. DD-19 respectively. After changing the effective edge by modifying key input interrupt 1 edge selection register, the value of P14 event register and interrupt request bit may become "1". A dummy write to the P14 event register and a clear to the interrupt request bit should be done after changing the effective edge. Same as key input interrupt edge selection register, when enabling/disabling key input interrupt 1 by setting key input interrupt 1 enable register, the value of P14 event register and interrupt request bit may become "1". A dummy write to the P14 event register and a clear to the interrupt request bit should be done after the setting of enabling/disabling.
P14 event register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KIN1EV
Address 02F616
When reset 0016
Bit symbol
KIN1EV0 KIN1EV1 KIN1EV2 KIN1EV3 KIN1EV4 KIN1EV5 KIN1EV6 KIN1EV7
Bit name
P14 event bit0 P14 event bit1 P14 event bit2 P14 event bit3 P14 event bit4 P14 event bit5 P14 event bit6 P14 event bit7
Function
0 : Without event 1 : with an event 0 : Without event 1 : with an event 0 : Without event 1 : with an event 0 : Without event 1 : with an event 0 : Without event 1 : with an event 0 : Without event 1 : with an event 0 : Without event 1 : with an event 0 : Without event 1 : with an event
R W(Note)
Note : The register is "0" cleared by dummy write.
Fig.DD-16 P14 event register
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Key input interrupt 1 enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KIN1EN
Address 02F416
When reset 0016
Bit Symbol
KIN1EN0 KIN1EN1 KIN1EN2 KIN1EN3 KIN1EN4 KIN1EN5 KIN1EN6 KIN1EN7
Bit name
Function
RW
0 : Disable Key input interrupt 1 enable bit 0 1 : Enable 0 : Disable Key input interrupt 1 enable bit 1 1 : Enable 0 : Disable Key input interrupt 1 enable bit 2 1 : Enable 0 : Disable Key input interrupt 1 enable bit 3 1 : Enable 0 : Disable Key input interrupt 1 enable bit 4 1 : Enable 0 : Disable Key input interrupt 1 enable bit 5 1 : Enable Key input interrupt 1 enable bit 6 0 : Disable 1 : Enable Key input interrupt 1 enable bit 7 0 : Disable 1 : Enable
Key input interrupt 1 edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KIN1SEL
Address 02F516
When reset 0016
Bit Symbol
KIN1SEL0 KIN1SEL1 KIN1SEL2 KIN1SEL3 KIN1SEL4 KIN1SEL5 KIN1SEL6 KIN1SEL7
Bit name Key input interrupt 1 edge selection bit 0 Key input interrupt 1 edge selection bit 1 Key input interrupt 1 edge selection bit 2 Key input interrupt 1 edge selection bit 3 Key input interrupt 1 edge selection bit 4 Key input interrupt 1 edge selection bit 5 Key input interrupt 1 edge selection bit 6 Key input interrupt 1 edge selection bit 7
Function 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge
RW
Fig.DD-17 Key input interrupt 1 registers
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Key input interrupt 1 control register (Address 005C16) P147 direction register Interrupt control circuit Key input interrupt 1 request Key input interrupt 1 edge selection bit7 P147 event latch circuit Event data Event register D Q DB7 S Q The read from address 02F616
Edge selection one-shot generation circuit
M16C/6K9 Group
Fig.DD-18 The block diagram of key input interrupt 1
RESET The read from address 02F616 R The read from address 02F616 R Q D R Delay circuit The read from address 02F616 Key input interrupt 1 edge selection bit6
Edge selection one-shot generation circuit
Jun 06, 2003
The read from address 02F616 P146 event latch circuit The write to address 02F616 The read from address 02F616 P145 event latch circuit The write to address 02F616 The read from address 02F616 P144 event latch circuit The write to address 02F616 The read from address 02F616 P143 event latch circuit The write to address 02F616 The read from address 02F616 P142 event latch circuit The write to address 02F616 The read from address 02F616 P141 event latch circuit The write to address 02F616 The read from address 02F616 P140 event latch circuit The write to address 02F616 The read from address 02F616 DB6 The read from address 02F616 DB5 The read from address 02F616 DB4 Key input interrupt 1 edge selection bit5
Edge selection one-shot generation circuit
Pull-up transistor
Pull-up selection bit
Key input interrupt 1 enable bit 7
Interrupt
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Key input interrupt 1 edge selection bit4
Edge selection one-shot generation circuit
P147/KI17
Pull-up transistor
Key input interrupt 1 enable bit 6
P146/KI16
Pull-up transistor
Key input interrupt 1 enable bit 5
P145/KI15
Pull-up transistor
Key input interrupt 1 enable bit 4
P144/KI14 Key input interrupt 1 edge selection bit3
Edge selection one-shot generation circuit
Pull-up transistor Key input interrupt 1 edge selection bit2
Edge selection one-shot generation circuit
Key input interrupt 1 enable bit 3
The read from address 02F616 DB3
P143/KI13
Pull-up transistor
Key input interrupt 1 enable bit 2
The read from address 02F616 DB2 The read from address 02F616 DB1
P142/KI12 Key input interrupt 1 edge selection bit1
Edge selection one-shot generation circuit
Pull-up transistor Key input interrupt 1 edge selection bit0
Edge selection one-shot generation circuit
Key input interrupt 1 enable bit 1
P141/KI11
Pull-up transistor
Key input interrupt 1 enable bit 0
The read from address 02F616 DB0
P140/KI10
M16C/6K9 Group
Interrupt
P140 P141 (Note 1)
P140 request P141 request
Interrupt request bit P140 event data (Note 2) P141 event data P14 event register 0016
0116
0316
0016
The read signal from 02F616 The read from 02F616 Interrupt procession
0116
0316 Interrupt procession
0016 Interrupt procession
Note 1: If there are several effective edge inputs, the input sequential order can not be confirmed. Note 2: If another interrupt request occurs between the setting of prior key input interrupt 1 request bit and the read of P14 event register, the interrupt request bit will be set again same as P14 event register. After the read of P14 event register, both the bits, which were set to "1", will be automatically cleared. However, the interrupt processing will be executed twice because of the re-setting of interrupt request bit (the value of P14 event register in the 2nd reading will be "0").
Fig.DD-19 The timing of key input interrupt 1
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Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The stacked value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Fig.DD-20 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt
Values that can be set R W 0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Fig.DD-20 Address match interrupt-related registers
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Precautions for Interrupts (1) Reading address 0000016
* When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets the request bit, which the interrupt source is enabled with the highest priority, to "0". Though the interrupt is generated, the interrupt routine may not be executed. Hence do not read address 0000016 by software.
(2) Setting the stack pointer
* The value of the stack pointer is initialized to 000016 right after the reset. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the _______ stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts _______ including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______
* As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pullup) if unused. Be sure to work on it. _______ * The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ * Do not reset the CPU with the input to the NMI pin being in the "L" state. _______ * Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to the _______ NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down. _______ * Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to the _______ NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ * Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
* Either an "L" level or an "H" level of at least 380 ns width is necessary for the signal input to pins INT0 _________ through INT11 regardless of the CPU operation clock. ________ _________ * When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Fig.DD-21 shows the procedure for changing ______ the INT interrupt generate factor.
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Clear the interrupt enable flag to "0" (Disable interrupt)
Set the interrupt priority level to level 0 (Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to "1" (Enable interrupt)
______
Fig.DD-21 Switching condition of INT interrupt request (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occurs, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: * When a instruction to rewrite the interrupt control register is executed when the interrupt is disabled, the
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
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Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. With XIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 32.7 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Fig.DG-1 shows the block diagram of the watchdog timer. Fig.DG-2 shows the watchdog timer-related registers.
Prescaler
"CM07 = 0" "WDC7 = 0"
1/16
BCLK HOLD
1/128
"CM07 = 0" "WDC7 = 1"
Watchdog timer
Watchdog timer interrupt request
"CM07 = 1"
1/2
Write to the watchdog timer start register (address 000E16) RESET
Set to "7FFF16"
Fig.DG-1 Block diagram of watchdog timer
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Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC Bit symbol
Address 000F16 Bit name
When reset 000XXXXX2 Function RW
High-order bit of watchdog timer Reserved bit Reserved bit
WDC7
Must always be set to "0" Must always be set to "0" Prescaler select bit 0 : Divided by 16 1 : Divided by 128
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate RW
Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written.
Fig.DG-2 Watchdog timer control and start registers
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M16C/6K9 Group
DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit) data transfer can be performed at high speed. Fig.EC-1 shows the block diagram of the DMAC. Table.EC-1 shows the DMAC specifications. Fig.EC-2 to EC-4 show the registers used by the DMAC.
Address bus
DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
(addresses 002916, 002816) DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816) DMA1 transfer counter TCR1 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Fig.EC-1 Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts neither. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit.
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DMAC
Table.EC-1 DMAC specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space * From any address in the 1M bytes space to a fixed address * From a fixed address to any address in the 1M bytes space * From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________ ________
Falling edge of INT0 or INT1 or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrupt requests A-D conversion interrupt requests IBF0 to IBF3 interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode * Single transfer mode After the transfer counter underflows, the DMA enable bit turns to "0", and the DMAC turns inactive * Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a "0" is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to "1", the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive * When the DMA enable bit is set to "0", the DMAC is inactive. * After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, the Forward address pointer and value of one of source pointer and destination pointer - the one specified for the reload timing for transfer forward direction - is reloaded to the forward direction address pointer, and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level.
DMA request factors (Note)
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DMAC
DMA0 request factor selection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL
Bit symbol
Address 03B816 Bit name
When reset 0016 Function
b3 b2 b1 b0
R
W
DSEL0
DMA request factor selection bits
DSEL1
DSEL2
DSEL3
0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit (DMS=0) /IBF0(DMS=1) 1 0 1 1 : UART0 receive (DMS=0) /IBF1(DMS=1) 1 1 0 0 : UART2 transmit (DMS=0) /IBF2(DMS=1) 1 1 0 1 : UART2 receive(DMS=0) /IBF3(DMS=1) 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMS DSR
DMA request factor expansion bit Software DMA request bit
0 : Normal 1 : Expanded factor If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
Fig.EC-2 DMAC register (1)
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M16C/6K9 Group
DMAC
DMA1 request factor selection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM1SL Bit name
Address 03BA16
When reset 0016 Function
b3 b2 b1 b0
Bit symbol
R
W
DSEL0
DMA request factor selection bits
DSEL1
DSEL2
DSEL3
0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit (DMS=0) /IBF0(DMS=1) 1 0 1 1 : UART0 receive (DMS=0) /IBF1(DMS=1) 1 1 0 0 : UART2 transmit(DMS=0) /IBF2(DMS=1) 1 1 0 1 : UART2 receive(DMS=0) /IBF3(DMS=1) 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMS DSR
DMA request factor expansion bit Software DMA request bit
0 : Normal 1 : Expanded factor If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMiCON(i=0,1) Bit symbol DMBIT DMASL DMAS DMAE DSD DAD
Address 002C16, 003C16 Bit name
When reset 00000X002 Function R W
Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3)
0 : 16 bits 1 : 8 bits 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward
(Note 2)
Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: DMA request can be cleared by resetting the bit to "0". Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously.
Fig.EC-3 DMAC register (2)
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M16C/6K9 Group
DMAC
DMAi source pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1
Address 002216 to 002016 003216 to 003016 Transfer count specification
When reset Indeterminate Indeterminate
Function * Source pointer Stores the source address
RW
0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMAi destination pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1
Address 002616 to 002416 003616 to 003416 Transfer count specification
When reset Indeterminate Indeterminate RW
Function * Destination pointer Stores the destination address
0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMAi transfer counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1
Address 002916, 002816 003916, 003816
When reset Indeterminate Indeterminate RW
Function * Transfer counter Set a value one less than the transfer count
Transfer count specification 000016 to FFFF16
Fig.EC-4 DMAC register (3)
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M16C/6K9 Group
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. * Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. Fig.EC-5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table.EC-2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table.EC-2 No. of DMAC transfer cycles Transfer unit 8-bit transfers (DMBIT= "1") 16-bit transfers (DMBIT= "0") Bus width 16-bit (BYTE= "L") 16-bit (BYTE= "L") Access address Even Odd Even Odd Single-chip mode No. of read No. of write cycles cycles 1 1 1 1 1 1 2 2
Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2
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DMAC
(1) 8-bit transfers 16-bit transfers from even address and the source address is even.
BCLK Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
(2) One wait is inserted into the source read under the conditions in (1)
BCLK Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
Note: The same thing changes occur with the respective conditions at the destination as at the source.
Fig.EC-5 Example of the transfer cycles for a source read
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M16C/6K9 Group
DMAC
DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately just before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately just before the transfer starts.
(2) External factors
An external factor is a factor caused to occur by the edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the falling edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately just before data transfer starts similarly to the state in which an internal factor is selected.
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M16C/6K9 Group
DMAC
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on the same sampling cycle (a sampling cycle means one period from the rising edge to the falling edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Fig.EC-6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur. BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Obtaining the bus right
Fig.EC-6 An example of DMA transfer effected by external factors
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M16C/6K9 Group
Timer
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Fig.FB-1 and FB-2 show the block diagram of timers.
Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32
* Timer mode * One-shot mode * PWM mode
f1 f8 f32
XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1"
1/32 Reset
fC32
Timer A0 interrupt Timer A0
TA0IN
Noise filter
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A1 interrupt Timer A1
TA1IN
Noise filter
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A2 interrupt Timer A2
TA2IN
Noise filter
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A3 interrupt Timer A3
TA3IN
Noise filter
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A4 interrupt TA4IN
Noise filter
Timer A4
* Event counter mode
Timer B2 overflow
Note 1: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin, so be careful.
Fig.FB-1 Timer A block diagram
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M16C/6K9 Group
Timer
Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 Timer A f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" 1/32 Reset fC32
* Timer mode * Pulse width measuring mode
TB0IN
Noise filter
Timer B0 interrupt
Timer B0
* Event counter mode
* Timer mode * Pulse width measuring mode
TB1IN
Noise filter
Timer B1 interrupt
Timer B1
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B2 interrupt
TB2IN
Noise filter
Timer B2
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B3 interrupt
TB3IN
Noise filter
Timer B3
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B4 interrupt
TB4IN
Noise filter
Timer B4
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B5 interrupt
TB5IN
Noise filter
Timer B5
* Event counter mode
Note 1: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin, so be careful.
Fig.FB-2 Timer B block diagram
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M16C/6K9 Group
Timer A
Timer A
Fig.FB-3 shows the block diagram of timer A. Fig.FB-4 to FB-6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer continually outputs pulse with arbitrary width.
Data bus high-order bits
Clock source selection
f1 f8 f32 fC32
Polarity selection
* Timer * One shot * PWM * Timer (gate function) * Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Counter (16) Clock selection
Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
TAiIN (i = 0 to 4)
Count start flag
(Address 038016)
TB2 overflow TAj overflow
(j = i - 1. Note, however, that j = 4 when i = 0) External trigger
Down count
Up/down flag
(Address 038416)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
TAiOUT
(i = 0 to 4)
Pulse output
Toggle flip-flop
Fig.FB-3 Block diagram of timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TAiMR(i=0 to 4)
Address When reset 039616 to 039A16 0016
Bit symbol
TMOD0
Bit name
b1 b0
Function
0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
Operation mode selection bits 0 0 : Timer mode
TMOD1
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source selection bits (Function varies with each operation mode)
Fig.FB-4 Timer A-related registers (1)
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M16C/6K9 Group
Timer A
Timer Ai register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 TA3 TA4
Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Function * Timer mode Count the internal count source * Event counter mode Count pulses from external input or the overflow of timer * One-shot timer mode Count one shot width * Pulse width modulation mode (16-bit PWM) Function as a 16-bit pulse width modulator * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator
Values that can be set
RW
000016 to FFFF16 000016 to FFFF16
000016 to FFFF16
000016 to FFFE16 0016 to FE16 (Both high-order and low-order addresses)
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function 0 : Stop count 1 : Start count
RW
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
When reset 0016
Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P
Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag
Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching factor
RW
Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal Timer A3 two-phase pulse processing enabled signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to "0"
Fig.FB-5 Timer A-related registers (2)
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M16C/6K9 Group
Timer A
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset 00X000002
Bit symbol
TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag
Function 1 : Timer start When read, the value is "0"
RW
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. TA0TGL TA0TGH
Timer A0 event/trigger selection bits
b7 b6
0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to "0".
Trigger selection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA1TGL
Bit name Timer A1 event/trigger selection bits
b1 b0
Function 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected
b3 b2
RW
TA1TGH
TA2TGL
Timer A2 event/trigger selection bits
TA2TGH
0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected
b5 b4
TA3TGL TA3TGH
Timer A3 event/trigger selection bits
0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected
b7 b6
TA4TGL TA4TGH
Timer A4 event/trigger selection bits
0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF Bit symbol
Address 038116 Bit name
When reset 0XXXXXXX2 Function RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Fig.FB-6 Timer A-related registers (3)
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Timer A
(1) Timer mode In this mode, the timer counts an internally generated count source. (See Table.FB-1) Fig.FB-7 shows the timer Ai mode register in timer mode. Table.FB-1 Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f8, f32, fC32 * Down count * When the timer underflows, it reloads the reload register contents and then continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) * Gate function Counting can be started and stopped by the TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed
Select function
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0
Address When reset 039616 to 039A16 0016 Bit name Function
b1 b0
RW
Operation mode selection bits Pulse output function selection bit
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
b4 b3
MR1
Gate function selection bits 0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
MR2
1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3) 0 (Must always be fixed to "0" in timer mode) Count source selection bits
b7 b6
MR3 TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0".
Fig.FB-7 Timer Ai mode register in timer mode
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M16C/6K9 Group
Timer A
(2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signals. Table.FB-2 lists timer specifications and Fig. FB-8 shows the timer Ai mode register in event count mode when counting a single-phase external signal. Table.FB-3 lists timer specifications and Fig. FB-8 shows the timer Ai mode register in event count mode when counting a two-phase external signals. Table.FB-2 Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source * External signal input to TAiIN pin (effective edge can be selected by software) * TB2 overflow, TAj overflow Count operation * Up count or down count can be selected by external signal or software * When the timer overflows or underflows, it reloads the reload register con tents and then continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TAiMR(i = 0, 1) Bit symbol TMOD0 TMOD1 MR0
Address 039616, 039716
When reset 0016 Function RW RW
Bit name Operation mode selection bits Pulse output function selection bit
b1 b0
0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4)
MR1 MR2 MR3 TCK0 TCK1
Count polarity selection bit (Note 3) Up/down switching factor selection bit
0 (Must always be fixed to "0" in event counter mode) Count operation type selection bit 0 : Reload type 1 : Free-run type
Invalid in event counter mode Can be "0" or "1"
Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0".
Fig.FB-8 Timer Ai mode register in event counter mode
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M16C/6K9 Group
Timer A
Table.FB-3 Timer specifications in event counter mode (when processing two-phase pulse signals with timers A2, A3, and A4) Item Count source Count operation Specification * Two-phase pulse signals input to TAiIN and TAiOUT pin * Up count or down count can be selected by two-phase pulse signals * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A2, A3, or A4 register * When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter * When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) * Normal processing operation The timer up-counts by the rising edge of TAiIN pin and down-counts by the falling edge fo TAiIN pin during the "H" level period of input signal in TAiOUT pin.
Divide ratio Count start condition Count stop condition
Interrupt request generation timing
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Select function
TAiOUT TAiIN (i=2,3)
Up count
Up count
Up count
Down count
Down count
Down count
* Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges Count down all edges
TAiIN (i=3,4)
Count up all edges Count down all edges
Note: This does not apply when the free-run function is selected.
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Timer A
Timer Ai mode register (When not using two-phase pulse signals' processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode selection bits Pulse output function selection bit
b1 b0
Function
0 1 : Event counter mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
RW
MR1 MR2 MR3 TCK0 TCK1
Count polarity selection bit 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges (Note 2) Up/down switching factor selection bit Count operation type selection bit Two-phase pulse signals' processing operation selection bit (Note 4)(Note 5) 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3)
0 : (Must always be "0" in event counter mode) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to "0". Note 4: This bit is valid for the timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0 "or "1". Note 5: When performing two-phase signal processing, make sure the two-phase pulse signals' processing operation selection bit (address 038416) is set to "1". Also, always be sure to set the event/trigger selection bit (addresses 038216 and 038316) to "00".
Timer Ai mode register (When using two-phase pulse signals' processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016
Bit symbol
TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Bit name
Operation mode selection bits
b1 b0
Function
0 1 : Event counter mode
RW
0 (Must always be "0" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) 1 (Must always be "1" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) Count operation type selection bit 0 : Reload type 1 : Free-run type
Two-phase pulse processing 0 : Normal processing operation operation selection bit 1 : Multiply-by-4 processing operation (Note 1)(Note 2)
Note 1: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0" or "1". Note 2: When performing two-phase pulse signals' processing, make sure the two-phase pulse signals' processing operation selection bit (address 038416) is set to "1". Also, always be sure to set the event/trigger selection bit (addresses 038216 and 038316) to "00".
Fig.FB-9 Timer Ai mode register in event counter mode
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M16C/6K9 Group
Timer A
(3) One-shot timer mode In this mode, the timer operates only once. (See Table.FB-4) When a trigger occurs, the timer starts to operate for a given period. Fig.FB-10 shows the timer Ai mode register in one-shot timer mode. Table.FB-4 Timer specifications in one-shot timer mode Item Specification Count source Count operation f1, f8, f32, fC32 * The timer counts down * When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value * An external trigger is input * The timer overflows * The one-shot start flag is set (= 1) * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)
Divide ratio Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode selection bits Pulse output function selection bit
b1 b0
Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3)
RW
MR1 MR2
External trigger selection bit (Note 2) Trigger selection bit
0 : One-shot start flag is valid 1 : Selected by event/trigger selection register
MR3 TCK0 TCK1
0 (Must always be "0" in one-shot timer mode) Count source selection bits
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger selection bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 3: Set the corresponding port direction register to "0".
Fig.FB-10 Timer Ai mode register in one-shot timer mode
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M16C/6K9 Group
Timer A
(4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table.FB-5) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Fig.FB-11 shows the timer Ai mode register in pulse width modulation mode. Fig.FB-12 shows the example of how a 16-bit pulse width modulator operates. Fig.FB-13 shows the example of how an 8-bit pulse width modulator operates. Table.FB-5 Timer specifications in pulse width modulation mode
Item
Count source Count operation
Specification
f1, f8, f32, fC32 * The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting * High level width n / fi n : Set value * Cycle time (216-1) / fi fixed * High level width n (m+1) / fi n : values set to timer Ai register's high-order address 8-1) (m+1) / fi * Cycle time (2 m : values set to timer Ai register's low-order address * External trigger is input * The timer overflows * The count start flag is set (= 1) * The count start flag is reset (= 0) The falling edge of PWM pulse Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)
16-bit PWM 8-bit PWM Count start condition
Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Address When reset 039616 to 039A16 0016 Function RW
Bit name Operation mode selection b1 b0 1 1 : PWM mode bits 1 (Must always be "1" in PWM mode)
External trigger selection 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) bit (Note 1) Trigger selection bit 0: Count start flag is valid 1: Selected by event/trigger selection register
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
MR3
16/8-bit PWM mode selection bit
TCK0 TCK1
Count source selection bits 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger selection bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding port direction register to "0".
Fig.FB-11 Timer Ai mode register in pulse width modulation mode
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M16C/6K9 Group
Timer A
Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected
1 / fi X (2 16 - 1)
Count source
TAiIN pin input signal
"H" "L"
Trigger is not generated by this signal 1 / fi X n
PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source Cleared to "0" when interrupt request is accepted, or cleared by software (f1, f8, f32, fC32) Note: n = 000016 to FFFE16.
Fig.FB-12 Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 8 - 1) Count source (Note1)
TAiIN pin input signal
"H" "L"
1 / fi X (m + 1) Underflow signal of 8-bit prescaler (Note2) "L"
"H"
1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32, fC32)
Cleared to "0" when interrupt request is accepted, or cleared by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FE16; n = 0016 to FE16.
Fig.FB-13 Example of how an 8-bit pulse width modulator operates
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M16C/6K9 Group
Timer B
Timer B
Fig.FB-14 shows the block diagram of timer B. Fig.FB-15 and FB-16 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits
Clock source selection
f1 f8 f32 fC32
TBiIN (i = 0 to 5)
* Timer * Pulse period/pulse width measurement
Reload register (16)
* Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i - 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5
Counter (16)
Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416
TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4
Fig.FB-14 Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited
R
W
Operation mode selection bits
MR0 MR1 MR2
Function varies with each operation mode
(Note 1) (Note 2)
MR3 TCK0 TCK1 Count source selection bits (Function varies with each operation mode)
Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5.
Fig.FB-15 Timer B-related registers (1)
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M16C/6K9 Group
Timer B
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1 TB2 TB3 TB4 TB5
Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
Function
* Timer mode Counts the timer's period * Event counter mode Counts external pulses input or a timer overflow * Pulse period / pulse width measurement mode Measures a pulse period or width
RW
000016 to FFFF16
000016 to FFFF16
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Timer B3, 4, 5 count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBSR
Address 034016
When reset 000XXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Fig.FB-16 Timer B-related registers (2)
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M16C/6K9 Group
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table.FB-6.) Fig.FB-17 shows the timer Bi mode register in timer mode. Table.FB-6 Timer specifications in timer mode Item Count source Count operation Specification f1, f8, f32, fC32 *Counts down *When the timer underflows, it reloads the reload register contents and then continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register *When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)
Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Bit name
Operation mode selection bits Invalid in timer mode Can be "0" or "1" 0 (Set to "0" in timer mode ; i = 0, 3)
b1 b0
Function
0 0 : Timer mode
R
W
(Note 1)
Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 2)
MR3
Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read in timer mode, turns out to be indeterminate. Count source selection bits
b7 b6
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5.
Fig.FB-17 Timer Bi mode register in timer mode
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M16C/6K9 Group
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table.FB-7) Fig.FB-18 shows the timer Bi mode register in event counter mode. Table.FB-7 Timer specifications in event counter mode Item Count source Specification *External signals input to TBiIN pin *Effective edge of count source can be a rising edge, a falling edge, or both edges as selected by software *Counts down *When the timer underflows, it reloads the reload register contents and then continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Count source input Count value can be read out by reading timer Bi register *When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter *When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)
Count operation
Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode selection bits Count polarity selection bits (Note 1)
b1 b0
Function
0 1 : Event counter mode
b3 b2
R
W
MR1
0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited
(Note 2)
MR2
0 (Fixed to "0" in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 3)
MR3
Invalid in event counter mode. In an attempt to write to this bit, write "0". The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be "0" or "1". Event clock selection 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow
(j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3)
TCK0 TCK1
Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be "0" or "1". Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to "0".
Fig.FB-18 Timer Bi mode register in event counter mode
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M16C/6K9 Group
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table.FB-8) Fig.FB-19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Fig.FB-20 shows the operation timing when measuring a pulse period. Fig.FB-21 shows the operation timing when measuring a pulse width. Table.FB-8 Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC32 *Up count *At measurement pulse's effective edge, after the count value is transferred to reload register, it is cleared to "000016" and then continues counting. Count start flag is set (= 1) Count start flag is reset (= 0) *When measurement pulse's effective edge is input (Note 1) *When an overflow occurs. (Simultaneously, the timer Bi overflow flag becomes "1". The timer Bi overflow flag becomes "0" when the count start flag is "1" and a value is written to the timer Bi mode register.) Measurement pulse input When timer Bi register is read, it indicates the reload register's content (measurement result) (Note 2) Cannot be written to
Count start condition Count stop condition Interrupt request generation timing
TBiIN pin function Read from timer Write to timer
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: After count starts, the value read out from the timer Bi register is indeterminate until the second effective edge is input .
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode selection bits Measurement mode selection bits
b1 b0
Function
1 0 : Pulse period / pulse width measurement mode
b3 b2
R
W
MR1
0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited
MR2
0 (Fixed to "0" in pulse period/pulse width measurement mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 2)
(Note 3)
MR3 TCK0 TCK1
Timer Bi overflow flag ( Note 1) Count source selection bits
0 : Timer did not overflow 1 : Timer has overflowed
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The timer Bi overflow flag becomes "0" when the count start flag is "1" and a value is written to the timer Bi mode register. This flag cannot be set to "1" by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5.
Fig.FB-19 Timer Bi mode register in pulse period/pulse width measurement mode
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M16C/6K9 Group
Timer B
When measuring a pulse time interval from falling edge to falling edge
Count source
Measurement pulse
"H" "L" Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter (Note 1) (Note 1) (Note 2)
Timing at which counter reaches "000016" Count start flag
"1" "0"
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Fig.FB-20 Operation timing when measuring a pulse period
Count source
Measurement pulse
"H" "L"
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timing at which counter reaches "000016" Count start flag
"1" "0"
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Fig.FB-21 Operation timing when measuring a pulse width
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M16C/6K9 Group
Serial I/O
Serial I/O
Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4.
UART0 to 2
Each of UART0 - UART2 has an exclusive timer to generate a transfer clock, operating independently from each other. Fig.GA-1 shows the block diagram of UART0, UART1 and UART2. Fig.GA-2 and GA-3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode selection bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table.GA-1 shows the comparison of functions of UART0 through UART2, and Fig.GA-4 to GA-8 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table.GA-1 Comparison of functions of UART0 through UART2
Function CLK polarity selection LSB first / MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Separate CTS/RTS pins Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection UART0 Possible Possible Possible Impossible Possible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) UART1 Possible Possible Possible Possible Impossible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) (Note 1) UART2 Possible Possible Possible Impossible Impossible Possible Impossible Possible N-channel open-drain output Possible Possible (Note 4) (Note 4) (Note 1) (Note 2) (Note 1)
Note 1: Only in clock synchronous serial I/O mode. Note 2: Only in clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only in UART mode. Note 4: Can be used for SIM interface.
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Serial I/O
(UART0)
RxD0
UART reception
TxD0
1/16
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A116)
Clock synchronous type
1/16
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (n0+1)
External
UART transmission
Clock synchronous type
Transmission control circuit
Transmit clock
Clock synchronous type
(when internal clock is selected)
1/2
CLK0
CLK polarity switching circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS disabled
CTS/RTS selected
RTS0
CTS0 / RTS0
Vcc CTS/RTS disabled CTS/RTS separated CTS0 from UART1
CTS0
(UART1)
RxD1
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A916)
1/16
TxD1
UART reception Reception control circuit Receive clock Transmit/ receive unit
Clock synchronous type UART transmission
1/16
1 / (n1+1)
External
Clock synchronous type Clock synchronous type
(when internal clock is selected) 1/2
Transmission control circuit
Transmit clock
CLK1 CTS1 / RTS1 / CTS0 / CLKS1
CLK polarity switching circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS disabled CTS/RTS separated Clock output pin select switch VCC CTS/RTS disabled CTS0
RTS1
CTS1
CTS0 to UART0 TxD polarity switching circuit Transmit/ receive unit
(UART2)
RxD2
RxD polarity switching circuit
UART reception
1/16
TxD2
Clock source selection Bit rate generator f1 Internal (address 037916) f8 f32 1 / (n2+1) External
Clock synchronous type UART transmission
1/16
Reception control circuit
Receive clock
Clock synchronous type Clock synchronous type
1/2
Transmission control circuit
Transmit clock
(when internal clock is selected)
CLK2
CLK polarity switching circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS selected
CTS/RTS disabled
RTS2
Vcc CTS/RTS disabled
CTS2 / RTS2
CTS2
n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2)
Fig.GA-1 Block diagram of UARTi (i = 0 to 2)
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Serial I/O
Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits)
1SP
PAR disabled
UART (7 bits)
UARTi receive register
RxDi
SP 2SP
SP
PAR
PAR enabled
UART
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART (8 bits) UART (9 bits)
UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16
UART (9 bits)
PAR enabled
Clock synchronous type
2SP SP SP 1SP
PAR
PAR disabled
UART
TxDi
Clock synchronous type
UART (7 bits)
UART (7 bits) UART (8 bits) Clock synchronous type
UARTi transmit register
"0"
SP: Stop bit PAR: Parity bit
Fig.GA-2 Block diagram of UARTi (i = 0, 1) transmit/receive unit
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Serial I/O
No reverse
RxD2
RxD data reverse circuit
Reverse
Clock synchronous type
1SP SP 2SP SP
PAR
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
UART2 receive register
PAR enabled
UART
UART (9 bits)
Clock synchronous type
UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 receive buffer register Address 037E16 Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
UART (8 bits) UART (9 bits)
D6
D5
D4
D3
D2
D1
D0
UART2 transmit buffer register Address 037A16 Address 037B16
2SP SP SP 1SP
PAR
PAR enabled
UART
UART (9 bits)
Clock synchronous type
PAR disabled
Clock synchronous type
"0"
UART (7 bits) UART (8 bits)
Clock synchronous type
UART(7 bits)
UART2 transmit register
Error signal output disable
Not reverse
Error signal output circuit
Error signal output enable Reverse
TxD data reverse circuit
TxD2
SP: Stop bit PAR: Parity bit
Fig.GA-3 Block diagram of UART2 transmit/receive unit
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Serial I/O
UARTi transmit buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16
When reset Indeterminate Indeterminate Indeterminate Function RW
Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turn out to be indeterminate.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB U2RB
Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16
When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data RW
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". OER FER PER SUM Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode selection bits (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out.
UARTi bit rate generator
b7 b0
Symbol U0BRG U1BRG U2BRG
Address 03A116 03A916 037916 Function
When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n+1
Fig.GA-4 Serial I/O-related registers (1)
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Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
Serial I/O mode selection bits
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock (Note 1) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
CKDIR Internal/external clock selection bit STPS PRY Stop bit length selection bit
0 : Internal clock 1 : External clock (Note 1) Invalid
Odd/even parity selection Invalid bit Parity enable bit Sleep selection bit Invalid Must always be "0"
PRYE SLEP
Note 1: Set the corresponding port direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
Serial I/O mode selection bits
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock (Note 1) Invalid
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited Must always be "0" 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Not reverse 1 : Reverse Usually set to "0"
CKDIR Internal/external clock selection bit STPS PRY Stop bit length selection bit
Odd/even parity selection Invalid bit
PRYE IOPOL
Parity enable bit TxD, RxD I/O polarity switching bit
Invalid 0 : Not reverse 1 : Reverse Usually set to "0"
Note 1: Set the corresponding port direction register to "0".
Fig.GA-5 Serial I/O-related registers (2)
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M16C/6K9 Group
Serial I/O
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS
Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode)
b1 b0 b1 b0
Bit name BRG count source selection bits
Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
CTS/RTS function selection bit
TXEPT
0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) 1 : No data present in transmit flag 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (Pins function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (Pins function as programmable I/O port) 1 : TXDi pin is N-channel opendrain output falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
NCH
Data output selection bit 0 : TXDi pin is CMOS output
CKPOL
CLK polarity selection bit 0 : Transmit data is output at
Must always be "0"
UFORM Transfer format selection 0 : LSB first 1 : MSB first bit
Must always be "0"
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function selection bit
Address 037C16
When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode)
b1 b0
Bit name BRG count source selection bits
RW
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0"
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 1 : RTS function is selected (Note 2)
TXEPT
0 : Data present in transmit register Transmit register empty 0 : Data present in transmit register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register register (transmission completed) (transmission completed)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 1 : CTS/RTS function disabled (Pins function programmable (Pins function programmable I/O port) I/O port) 0 : TXDi pin is CMOS output 0: TXDi pin is CMOS output
Nothing is assigned.
CKPOL
1: : TXDi pin is N-channel In an attempt to write to this bit, write1"0". The value, if read, turns out TXDi pin is N-channel to be "0". open-drain output open-drain output 0 : Transmit data is output at Must always be "0" CLK polarity selection bit falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
UFORM Transfer format selection 0 : LSB first bit (Note 3) 1 : MSB first
0 : LSB first 1 : MSB first
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Fig.GA-6 Serial I/O-related registers (3)
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Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register Receive enable bit Receive complete flag 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RE RI
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1
Address 037D16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Invalid
RW
Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register Receive enable bit Receive complete flag 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : Not reverse 1 : Reverse Must be fixed to "0"
RE RI
U2IRS
UART2 transmit interrupt factor selection bit
U2RRM UART2 continuous receive mode enable bit
U2LCH Data logic selection bit U2ERE Error signal output enable bit
0 : Not reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
Fig.GA-7 Serial I/O-related registers (4)
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Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON Bit symbol U0IRS
Address 03B016
When reset X00000002 Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
Bit name UART0 transmit interrupt factor selection bit UART1 transmit interrupt factor selection bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
RW
U1IRS
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enabled
Invalid
0 : Continuous receive mode disabled 1 : Continuous receive mode enabled CLKMD0 CLK/CLKS selection bit 0 Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 CLKMD1 CLK/CLKS selection bit 1 0 : Normal mode (CLK output is CLK1 only) (Note) 1 : Transfer clock output from multiple pins function selected RCSP Separate CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated
U1RRM UART1 continuous receive mode enable bit
Invalid
Invalid
Must always be "0"
0 : CTS/RTS shared pin 1 : CTS/RTS separated
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock selection bit (bit 3 at address 03A816) = "0".
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
0000
Bit symbol
Symbol U2SMR
Address 037716
When reset 0016 Function (During UART mode)
Bit name
Function (During clock synchronous serial I/O mode) Must always be "0" Must always be "0"
RW
Reserved bits ABSCS Bus collision detect sampling clock selection bit Auto clear function selection bit of transmit enable bit Transmit start condition selection bit
0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2
ACSE
Must always be "0"
SSS
Must always be "0"
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".
Fig.GA-8 Serial I/O-related registers (5)
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M16C/6K9 Group
Serial I/O
Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables.GA-2 and GA-3 list the specifications of the clock synchronous serial I/O mode. Fig.GA-9 shows the UARTi transmit/ receive mode register. Table.GA-2 Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format * Transfer data length: 8 bits Transfer clock * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "1") : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control * Selecting from CTS function/RTS function/Disable CTS, RTS function Transmission start condition * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _______ _______ _ When CTS function selected, CTS input level = "L" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" Reception start condition * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" * When transmitting _ Transmit interrupt factor selection bits (bits 0, 1 at address 03B016, bit 4 at Interrupt request address 037D16) = "0": At the completion of data transmission from UARTi generation timing transfer buffer register to UARTi transmit register _ Transmit interrupt factor selection bits (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "1": At the completion of data transmission from UARTi transfer register is completed * When receiving _ At the completion of data transferring from UARTi receive register to UARTi receive buffer register Error detection * Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1".
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M16C/6K9 Group
Serial I/O
Clock synchronous serial I/O mode
Table.GA-3 Specifications of clock synchronous serial I/O mode (2) Item Function selection Specification * CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) (Note) UART1 transfer clock can be chosen by software to be output from one of the two pins set
_______ _______
* Separate CTS/RTS pins (UART0) (Note) _______ _______ Each of UART0 CTS and RTS pins can be assigned to separate pins * Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. * TxD, RxD I/O polarity switching (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
_______ _______
Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be selected simultaneously.
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M16C/6K9 Group
Serial I/O
Clock synchronous serial I/O mode
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP
Address 03A016, 03A816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode selection bits
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 1)
Internal/external clock selection bit
Invalid in clock synchronous serial I/O mode 0 (Must always be "0" in clock synchronous serial I/O mode)
Note 1: The corresponding port direction register should be "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL
Address 037816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode selection bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 2)
Internal/external clock selection bit
Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse
Note 1: Usually sent to "0". Note 2: The corresponding port direction register should be "0".
Fig.GA-9 UARTi transmit/receive mode register in clock synchronous serial I/O mode
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Serial I/O
Clock synchronous serial I/O mode
Table.GA-4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table _______ _______ shows the pin functions that the transfer clock output from multiple pins and the separation of CTS/RTS pins are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table.GA-4 Input/output pin functions in clock synchronous serial I/O mode (The function that the transfer clock output from multiple pin is not selected. The function that separates CTS/RTS pins is not selected.)
Pin name TxDi RxDi Function Serial data output Serial data input Method of selection (Outputs dummy data when performing reception only) The corresponding bit of port direction register = "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" The corresponding bit of port direction register = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" The corresponding port direction bit = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1"
CLKi
Transfer clock output Transfer clock input
CTSi/RTSi
CTS input
RTS output Programmable I/O port
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Clock synchronous serial I/O mode
* Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1" "0" "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" Data is set in UARTi transmit buffer register
Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi
"L"
TCLK
Stopped because CTS = "H"
Stopped because transfer enable bit = "0"
CLKi
TxDi Transmit register empty flag (TXEPT)
"1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transmit interrupt "1" "0" request bit (IR) Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity selection bit = "0". * Transmit interrupt factor selection bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi
* Example of receive timing (when external clock is selected)
Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi
"1" "0" "1" "0" "1" "0" "H" "L"
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in D0 D1 D2 D3 D4 D5 D6 D7 "1"
Transferred from UARTi receive register to UARTi receive buffer register
RxDi Receive complete "0" flag (Rl) Receive interrupt request bit (IR)
"1" "0"
D0 D1 D2
D3 D4 D5
Read out from UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity selection bit = "0". fEXT: frequency of external clock The following conditions should be matched when the input level of CLKi pin is "H" before the data reception. * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register
Fig.GA-10 Typical transmit/receive timings in clock synchronous serial I/O mode
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Clock synchronous serial I/O mode
(a) Polarity selection function As shown in Fig.GA-11, the CLK polarity selection bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows to select the polarity of the transfer clock.
* When CLK polarity selection bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 1: The CLK pin level is "H" when there is no transferring.
* When CLK polarity select bit = "1"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 2: The CLK pin level is "L" when there is no transferring.
Fig.GA-11 Polarity of transfer clock (b) LSB first/MSB first selection function As shown in Fig.GA-12, when the transfer format selection bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
* When transfer format selection bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7
LSB first
D7
* When transfer format selection bit = "1"
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0
MSB first
D0
Note: This applies when the CLK polarity selection bit = "0".
Fig.GA-12 Transfer format
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Serial I/O
Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function (UART1) This function allows to set two transfer clock output pins and chooses one to output a clock by the setting of CLK and CLKS selection bits (bits 4 and 5 at address 03B016). (See Fig.GA-13) The function is valid only _______ _______ when the UART1 internal clock is selected. Note that when this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1
CLKS1 CLK1 IN CLK IN CLK
Fig.GA-13 The sample of transfer clock output from the multiple pins function (d) Continuous receive mode If the continuous receive mode enable bits (bits 2 and 3 at address 03B016, bit 5 at address 037D16) are set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0) This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method of setting and the input/output pin functions are both the same, so refer to the selection function in the next section, "(2) Clock asynchronous serial I/O (UART) mode." Note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) Serial data logic switch function (UART2) When the data logic selection bit (bit6 at address 037D16) = "1", the data writing to transmit buffer register or reading from receive buffer register, are reversed. Fig.GA-14 shows the example of serial data logic switch timing.
*When LSB first
Transfer clock TxD2 TxD2
"H" "L" "H"
(no reverse) "L"
"H"
D0
D1
D2
D3
D4
D5
D6
D7
(reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
Fig.GA-14 Serial data logic switch timing
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Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables.GA-5 and GA-6 list the specifications of the UART mode. Fig.GA-15 shows the UARTi transmit/receive mode register. Table.GA-5 Specifications of UART Mode (1) Specification * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected Transfer clock * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816 ="1") : fEXT/16(n+1)(Note 1) (Note 2) * Do not select the external clock in UART2. _______ _______ _______ _______ Transmission/reception control * Selecting from CTS function/ RTS function/ Disable CTS, RTS function Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _______ _______ - When CTS function is selected CTS input level = "L" Reception start condition * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" - Start bit detection Interrupt request * When transmitting generation timing - Transmit interrupt factor selection bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": At the completion of data transferring from UARTi transfer buffer register to UARTi transmit register - Transmit interrupt factor selection bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": At the completion of data transmission from UARTi transfer register * When receiving - At the completion of data transferring from UARTi receive register to UARTi receive buffer register Error detection * Overrun error (Note 3) This error occurs when the bit prior to the stop bit of next data is received before the contents of UARTi receive buffer register are read out. * Framing error This error occurs when the number set for stop bits is not detected * Parity error This error occurs in the case that parity is enabled and the number of "1" in parity bit and character bits does not match the number of "1" in parity odd/ even setting. * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate register. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Also note that the UARTi receive interrupt request bit is not set to "1". Item Transfer data format
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Table.GA-6 Specifications of UART Mode (2) Item
_______ _______
Specification * Separate CTS/RTS pins (UART0) _______ _______ Each of UART0 CTS and RTS pins can be assigned to separate pins * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit,and stop bit are not reversed. * TXD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level are reversed.
Function selection
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UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode selection bits
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock (Note 1) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
RW
Internal / external clock selection bit Stop bit length select bit Odd / even parity select bit
PRYE SLEP
Parity enable bit Sleep selection bit
Note 1: The corresponding port direction register should be "0".
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode selection bits
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Must always be "0" 0 : One stop bit 1 : Two stop bits
RW
Internal / external clock selection bit Stop bit length select bit
Odd / even parity selection bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity Parity enable bit TxD, RxD I/O polarity switching bit (Note) 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse
PRYE IOPOL
Note: Usually set to "0".
Fig.GA-15 UARTi transmit/receive mode register in UART mode
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Clock asynchronous serial I/O (UART) mode
Table.GA-7 lists the functions of the input/output pins during UART mode. This table shows the pin functions _______ _______ when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.)
________________
Table.GA-7 Input/output pin functions in UART mode (when CTS/RTS separate function is not selected)
Pin name TxDi RxDi CLKi Function Serial data output Serial data input Programmable I/O port Transfer clock input Corresponding port direction register bit = "0".(Can be used as an input port when performing transmission only) Internal/external clock selection bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock selection bit (bit 3 at address 03A016, 03A816) = "1" Corresponding port direction register bit = "0" (Don't select the external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Corresponding port direction register bit = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" Method of selection
CTSi/RTSi
CTS input
RTS output Programmable I/O port
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* Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L".
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register
"H"
CTSi
"L"
Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Parity bit
P
Stop bit
SP
Stopped because transmit enable bit = "0"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt factor selection bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
* Example of transmit timing when transfer data are 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0"
Stop bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit interrupt request bit (IR)
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt factor selection bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Fig.GA-16 Typical transmit timings in UART mode
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* Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in USAR2 transmit buffer register
Note1
Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Parity Stop bit bit
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt factor selection bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) n : value set to BRGi
Note1. According to the above timing, the transmission is started by the timing of BRG overflow after writing to the transmit buffer.
Fig.GA-17 Typical transmit timings in UART mode (UART2)
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* Example of receive timing when transfer data are 8 bits long (parity disabled, one stop bit)
BRGi count source Receive enable bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Transferred from UARTi receive register to UARTi receive buffer register
Stop bit
D0
D1
D7
Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected.
Fig.GA-18 Typical receive timing in UART mode
_______ _______
(a) Separate CTS/RTS pins function (UART0) _______ _______ _______ _______ Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" separates the RTS and CTS signals to _______ _______ _______ _______ different input/out pins.(Fig GA-19). Choosing one from CTS or RTS, by using of the CTS/RTS function selection bit (bit 2 of address 03A416). This function is effective in UART0 only. If the function is used, the _______ _______ _______ _______ user cannot use the CTS/RTS function of UART1. Set "0" both to the CTS/RTS function selection bit (bit 2 of _______ _______ address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16).
Microcomputer
TXD0 RXD0 IN OUT
IC
RTS0 CTS0
CTS RTS
Note : The user cannot use CTS and RTS at the same time.
_______ _______
Fig.GA-19 The separate CTS/RTS pins function usage (b) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected with UARTi. The sleep mode is selected when the sleep selection bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".
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(c) Function for switching serial data logic (UART2) When the data logic selection bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Fig.GA-20 shows the example of timing for switching serial data logic.
* When LSB first, parity enabled, one stop bit
Transfer clock TxD2
(no reverse)
"H" "L" "H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TxD2
(reverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit P : Even parity SP : Stop bit
Fig.GA-20 Timing for switching serial data logic
(d) TxD, RxD I/O polarity switching function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use. (e) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Fig.GA-21 shows the example of detection timing of a bus collision (in UART mode).
Transfer clock
"H" "L"
TxD2 RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit
"H" "L" "H" "L" "1" "0" "1" "0"
ST
SP
ST
SP
ST : Start bit SP : Stop bit
Fig.GA-21 Detection timing of a bus collision (in UART mode)
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(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card IC or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table.GA-8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Table.GA-8 Specifications of clock-asynchronous serial I/O mode (compliant with SIM I/F) Item Transfer data format Specification * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 037816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") * With the internal clock chosen (bit 3 of address 037816 = "0") : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 * Don't chose external clock.
_______ _______
Transfer clock
Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") Other settings * The sleep mode selection function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" Reception start condition * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit Interrupt request * When transmitting generation timing When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Also Note that the UARTi receive interrupt request bit is not set to "1".
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Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UART2 transmit buffer register
Note1
Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2 Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
RxD2 Signal conductor level (Note1) Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR)
"1" "0" "1" "0" ST D0 D1 D2 D3 D4 D5 D6 D7 P
A "L" level returns from TxD2 due to the occurrence of a parity error
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
The level is detected by the interrupt routine
The level is detected by the interrupt routine
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note 1. According to the above timing, the transmission is started by the timing of BRG overflow after writing to the transmit buffer.
Tc
Transfer clock Receive enable bit(RE)
"1" "0"
Start bit RxD2
Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
TxD2 Signal conductor level (Note 2) Receive complete flag (RI) Receive interrupt request bit (IR)
"1" "0" "1" "0" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
A "L" level returns from TxD2 due to the occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Read to receive buffer
Read to receive buffer
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note 2. The waveforms are the same because TxD2 and RxD2 are connected.
Fig.GA-22 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
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Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D16) assigned "1", an "L" level from the TxD2 pin will be output when a parity error is detected. Link with this function, the timing to generate a transmission completion interrupt varies according to the timing of a parity error signal detection. Fig.GA-23 shows the timing of the parity error signal output.
* LSB first
Transfer clock RxD2 TxD2 Receive complete flag
"H" "L" "H" "L" "H" "L" "1" "0"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Hi-Z
ST : Start bit P : Even parity SP : Stop bit
Fig.GA-23 Timing of the parity error signal output (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, data are output from TxD2 beginning with D0. If you choose the inverse format, data are inverted and output from TxD2 beginning with D7. Fig.GA-24 shows the SIM interface format.
Transfer clcck TxD2 (direct) TxD2 (inverse)
D0
D1
D2
D3
D4
D5
D6
D7
P
D7
D6
D5
D4
D3
D2
D1
D0
P P : Even parity
Fig.GA-24 SIM interface format
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Clock asynchronous serial I/O (UART) mode
Fig.GA-25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
SIM card TxD2 RxD2
Fig.GA-25 Connecting the SIM interface
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Clock asynchronous serial I/O (UART) mode
UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways. Fig.GA-26 shows the UART2 special mode register.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
0000
Bit symbol
Symbol U2SMR
Address 037716
When reset 0016 Function (During UART mode)
Bit name
Function (During clock synchronous serial I/O mode) Must always be "0" Must always be "0"
RW
Reserved bits ABSCS Bus collision detect sampling clock selection bit Auto clear function selection bit of transmit enable bit Transmit start condition selection bit Reserved bit
0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2
ACSE
Must always be "0"
SSS
Must always be "0" Must always be "0"
Fig.GA-26 UART2 special mode register
Some other functions added are explained here. Fig.GA-27 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock selection bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function selection bit of transmit enable bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition selection bit. Setting this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD pin.
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Clock asynchronous serial I/O (UART) mode
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function selection bit of transmit enable bit (Bit 5 of the UART2 special mode register)
CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit
3. Transmit start condition selection bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK TxD
Enabling transmission With "1: falling edge of RxD2" selected
CLK TxD RxD
Fig.GA-27 Some other functions added
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Clock asynchronous serial I/O (UART) mode
S I/O3, 4 S I/O3, 4
S I/O 3 and S I/O 4 are exclusive clock-synchronous serial I/Os. Fig.GA-28 shows the S I/O 3, 4 block diagram, and Fig.GA-29 shows the S I/O 3, 4 control register. Table.GA-9 shows the specifications of S I/O 3, 4.
f1 f8 f32
SMi1 SMi0
Data bus
Synchronous circuit SMi3 SMi6 SMi6
1/2
1/(ni+1)
Transfer rate register (8)
CLKi
S I/O counter i (3)
S I/Oi interrupt request
SMi2 SMi3 SMi5 LSB MSB
SOUTi SINi
S I/Oi transmission/reception register (8) 8 Note: i = 3, 4. ni = A value set in the S I/O transfer rate register i (036316, 036716).
Fig.GA-28 S I/O3, 4 block diagram
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Clock asynchronous serial I/O (UART) mode
S I/O3, 4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 Bit symbol
SMi0 SMi1 SMi2 SMi3
Symbol SiC
Address 036216, 036616 Bit name
When reset 4016 Description
b1 b0
RW
Internal synchronous clock selection bits
0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Not to be used
SOUTi output disable bit S I/Oi port selection bit (Note 2)
0 : SOUTi output 1 : SOUTi output disable (high impedance) 0 : Input-output port 1 : SOUTi output, CLK function Must be "0" 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output
Reserved bit SMi5 SMi6 SMi7 Transfer direction selection bit lect bitc Synchronous clock selection bit (Note 2) SOUTi initial value set bit
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When SI/Oi port selection bit (i= 3, 4) is set to "0" as for I/O port, set the synchronous clock selection bit to "1".
SI/Oi bit rate generator
b7 b0
Symbol S3BRG S4BRG
Address 036316 036716 Indeterminate
When reset Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n + 1
SI/Oi transmission/reception register
b7 b0
Symbol S3TRR S4TRR
Address 036016 036416 Indeterminate
When reset Indeterminate Indeterminate RW
Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input.
Fig.GA-29 S I/O3, 4 control registers
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Clock asynchronous serial I/O (UART) mode
S I/O3, 4
Table.GA-9 Specifications of S I/O3, 4 Item Transfer data format Transfer clock Specifications * Transfer data length: 8 bits * With the internal clock selected (bit 6 of 036216, 036616 = "1"): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) * With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2) * To start transmit/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616) - Write transfer data to SI/Oi transmission/reception register(036016, 036416) * To use S I/Oi interrupts, the following requirements must be met: - S I/Oi interrupt request bit (bit 3 of 004916, 004816) = 0. * At the rising edge of the last transfer clock (Note3) * LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. * The SOUTi default value setting function If the transfer clock is selected to external clock, the output level of SOUTi pin can be selected when it is not in transferring please refer to Fig.GA-30. * The SI/Oi (i=3,4) is different from UART0 to 2 that the register and buffer can not be separated, so don't write the next transfer data to the transmission/reception register(036016, 036416) during transferring. * If the transfer clock is selected to internal clock, at the end of transferring, the SOUTi holds the last data during the last 1/2 transfer clock, and then to high impedance. If the transmission/reception register(036016, 036416) is written during the period, the SOUTi becomes the high impedance right the writing ,the data hold time will be shortened.
Conditions for transmission/ reception start
Interrupt request generation timing Select function
Precaution
Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4). Note 2: With the external clock selected: * Please write to the SI/Oi transmission/reception register(036016, 036416) under the status that the CLKi pin is input to "H" level. Also please write to the bit 7(SOUTi default value setting bit) under the status that the CLKi pin is input to "H" level. * The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the "H" state.
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M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
S I/O3, 4 Functions for setting an SOUTi initial value
In carrying out transmission, the output level of the SOUTi pin as it is before transmitting 1-bit data can be set either to "H" or to "L". Fig.GA-30 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) With "H" selected for SOUTi
Signal written to the SI/Oi transmission /reception register SOUTi's initial value set bit (SMi7)
SI/Oi port selection bit SMi3 = 0
SOUTi initial value selection bit SMi7 = 1 "H" level) (SOUTi: Internal
SI/Oi port selection bit (SMi3)
SOUTi (internal)
D0
SI/Oi port selection bit SMi3 = 0 1 (Port selection: Normal port SOUTi)
SOUTi pin = "H" output
Port output SOUTi pin output
D0
Initial value = "H"(Note)
Signal written to the SI/Oi register ="L" "H" "L" (Falling edge )
(i = 3, 4)
Setting the SOUTi initial value to H
Port selection (normal port SOUTi)
Note: The set value is output only when the external clock has been selected. Please set the SOUTi default under the status that the CLKi is input to "H" level. If the internal clock has been selected or if SOUTi output inhibition has been set, this output goes to the high-impedance state.
SOUTi pin = Outputting stored data in the SI/Oi transmission/ reception register
Fig.GA-30 Timing chart for setting SOUTi's initial value and how to set it
S I/Oi operation timing
Fig.GA-31 shows the S I/Oi operation timing
MAX:1.5 cycle SI/Oi internal clock Transfer clock (Note 1) Signal written to the SI/Oi register (Note 2) S I/Oi output SOUTi (i= 3, 4) SI/Oi input SINi (i= 3, 4) SI/Oi interrupt "1" request bit (i=3,4) "0" Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the SI/Oi control register (i = 3,4). (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi (i = 3,4) pin becomes to the high-impedance state after the transfer finishes. Note 3: The figure shows when the port selection bit of SOUTi (i = 3,4) is set to "1". Hiz D0 D1 D2 D3 D4 D5 D6 D7 Hiz
Fig.GA-31 S I/Oi operation timing chart
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M16C/6K9 Group
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table.JA-1 shows the performance of the A-D converter. Fig.JA-1 shows the block diagram of the A-D converter, and Fig.JA-2 and JA-3 show the A-D converter-related registers. Table.JA-1 Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage 0V to AVCC (VCC) Operating clockAD (Note1) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision * 8-bit resolution 2LSB * 10-bit resolution 6LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) A-D conversion start condition * Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" * External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the ___________ ADTRG/P97 input changes from "H" to "L" Conversion speed per pin * Without sample and hold function 8-bit resolution : 49 AD cycles 10-bit resolution : 59 AD cycles * With sample and hold function 8-bit resolution : 28 AD cycles 10-bit resolution : 33 AD cycles Note 1: The frequency AD should be set to 250kHz min and 8MHz max. Without sample and hold function,set the AD frequency to 250kHz min. With the sample and hold fucntion, set the AD frequency to 1MHz min.
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A-D Converter
A-D conversion rate selection
CKS1=1
AD
CKS0=1
fAD
1/2
1/2
CKS0=0
CKS1=0
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16)
A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) Vref Decoder
VIN
Comparator
Data bus high-order
Data bus low-order
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111
OPA1, OPA0
OPA1,OPA0=0,0
OPA1,OPA0=0,1
ANEX0 ANEX1
OPA1,OPA0=1,0
0 0 1 1
0 : AN0-AN7 1 : ANEX0 0 : ANEX1 1 : Inhibited
Fig.JA-1 Block diagram of A-D converter
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M16C/6K9 Group
A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin selection bits
CH2 MD0 MD1 TRG ADST CKS0 Trigger selection bit A-D conversion start flag Frequency selection bit 0 A-D operation mode selection bits 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started
(Note 2)
0 : FAD/4 selected 1 : FAD/2 selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function RW
A-D sweep pin selection bits When single sweep and repeat sweep mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode selection bit 1 8/10-bit mode selection bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : FAD/2 or FAD/4 selected 1 : FAD selected 0 : Vref not connected 1 : Vref connected
b7 b6
BITS CKS1 VCUT OPA0
Frequency selection bit 1 Vref connect bit
ANEX0,1 selection bits OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig.JA-2 A-D converter-related registers (1)
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M16C/6K9 Group
A-D Converter
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol ADCON2 Bit symbol
SMP
Address 03D416 Bit name
When reset 000100002 Function
0 : Without sample and hold 1 : With sample and hold Must be "0". RW
A-D conversion method select bit
Reserved bits Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turn out to be "0".
A-D register i
(b15) b7 (b8) b0 b7
Symbol
ADi(i=0 to 7)
Address When reset 03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
RW
Fig.JA-3 A-D converter-related registers (2)
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A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin selection bits is used for one-shot A-D conversion. Table.JA-2 shows the specifications of one-shot mode. Fig.JA-4 shows the A-D control register in oneshot mode. Table.JA-2 One-shot mode specifications Item Specification Function The pin selected by the analog input pin selection bits is used for one A-D conversion Start condition Writing "1" to A-D conversion start flag Stop condition * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin One of AN0 to AN7, as selected Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin selection bits
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode selection bits 0 Trigger selection bit A-D conversion start flag Frequency selection bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2) (Note 2)
0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : FAD/4 selected 1 : FAD/2 selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0
Address 03D716 Bit name
When reset 0016 Function RW
A-D sweep pin selection Invalid in one-shot mode bits A-D operation mode selection bit 1 8/10-bit mode select bit 0 : Any mode other than repeat sweep mode 1
0 : 8-bit mode 1 : 10-bit mode 0 : FAD/2 or FAD/4 selected Frequency selection bit 1 1 : FAD selected Vref connect bit 1 : Vref connected
b7 b6
ANEX0,1 selection bis OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig.JA-4 A-D conversion register in one-shot mode
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M16C/6K9 Group
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin selection bits is used for repeated A-D conversion. Table.JA-3 shows the specifications of repeat mode. Fig.JA-5 shows the A-D control register in repeat mode. Table.JA-3 Repeat mode specifications Item Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin selection bits is used for repeated A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag Not generated One of AN0 to AN7, as selected Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
CH2 MD0 MD1 TRG ADST CKS0
Analog input pin selection 0 0 0 : AN0 is selected bits 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected A-D operation mode selection bits 0 Trigger selection bit A-D conversion start flag Frequency selection bit 0
b4 b3
(Note 2) (Note 2)
0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : FAD/4 selected 1 : FAD/2 selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0
Address 03D716 Bit name
When reset 0016 Function
Invalid in repeat mode RW
A-D sweep pin selection bits A-D operation mode selection bit 1 8/10-bit mode selection bit
Should be "0" in this mode
0 : 8-bit mode 1 : 10-bit mode 0 : FAD/2 or FAD/4 selected Frequency selection bit 1 1 : FAD selected 1 : Vref connected
b7 b6
Vref connect bit
ANEX0,1 selection bis OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig.JA-5 A-D conversion register in repeat mode
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M16C/6K9 Group
A-D Converter
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin selection bits are used for one-by-one AD conversion. Table.JA-4 shows the specifications of single sweep mode. Fig.JA-6 shows the A-D control register in single sweep mode. Table.JA-4 Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin selection bits are used for one-by-one A-D conversion Start condition Writing "1" to A-D converter start flag Stop condition * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converter Read A-D registers corresponding to selected pins
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in single sweep mode
RW
Analog input pin selection bits
A-D operation mode selection bits 0 Trigger selection bit A-D conversion start flag Frequency selection bit 0
b4 b3
1 0 : Single sweep mode
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : FAD/4 selected 1 : FAD/2 selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins)
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit
MD2 BITS CKS1 VCUT OPA0
Should be "0" in this mode
0 : 8-bit mode 1 : 10-bit mode 0 : FAD/2 or FAD/4 selected Frequency selection bit 1 1 : FAD selected Vref connect bit 1 : Vref connected
b7 b6
ANEX0,1 selection bis OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig.JA-6 A-D conversion register in single sweep mode
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A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin selection bits are used for repeat sweep A-D conversion. Table.JA-5 shows the specifications of repeat sweep mode 0. Fig.JA-7 shows the A-D control register in repeat sweep mode 0. Table.JA-5 Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin selection bits are used for repeat sweep A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag Not generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D registers corresponding to selected pins (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function RW
Analog input pin selection bits Invalid in repeat sweep mode 0
A-D operation mode selection 1 1 : Repeat sweep mode 0 bits 0 Trigger selection bit A-D conversion start flag Frequency selection bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : FAD/4 selected 1 : FAD/2 selected
b4 b3
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
b1 b0
RW
A-D sweep pin selection bits When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) A-D operation mode selection bits 1 8/10-bit mode selection bit Frequency selection bit 1 Vref connect bit Should be "0" in this mode 0 : 8-bit mode 1 : 10-bit mode 0 : FAD/2 or FAD/4 selected 1 : FAD selected 1 : Vref connected
b7 b6
SCAN1
MD2 BITS CKS1 VCUT OPA0
ANEX0,1 selection bis OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig.JA-7 A-D conversion register in repeat sweep mode 0
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A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin selection bits. Table.JA-6 shows the specifications of repeat sweep mode 1. Fig.JA-8 shows the A-D control register in repeat sweep mode 1. Table.JA-6 Repeat sweep mode 1 specifications Item Function Specification All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin selection bits Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag Not generated AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Read A-D registers corresponding to selected pins (at any time)
Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function RW
Analog input pin selection bits Invalid in repeat sweep mode 1
A-D operation mode selection 1 1 : Repeat sweep mode 1 bits 0 Trigger select bit A-D conversion start flag Frequency selection bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : FAD/4 selected 1 : FAD/2 selected
b4 b3
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When repeat sweep mode 1 is selected
b1 b0
RW
A-D sweep pin selection bits
SCAN1
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) A-D operation mode selection 1 : Repeat sweep mode 1 bit 1 0 : 8-bit mode 8/10-bit mode selection bit 1 : 10-bit mode Frequency selection bit 1 Vref connect bit 0 : FAD/2 or FAD/4 selected 1 : FAD selected 1 : Vref connected
b7 b6
MD2 BITS CKS1 VCUT OPA0
ANEX0,1 selection bis OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig.JA-8 A-D conversion register in repeat sweep mode 1
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A-D Converter
(a) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "0", input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is "0" and bit 7 is "1", input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1.
(b) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rage of conversion of each pin increases. As a result, a 28 AD cycle is achieved with 8-bit resolution and 33AD cycle with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.
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D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. DA conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the corresponding port to output mode if D-A conversion is to be performed. If D-A output is enabled, the pull-up of corresponding port is inhibited. Output analog voltage (V) is determined by a set value n (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table.JB-1lists the performance of the D-A converter. Fig.JB-1 shows the block diagram of the D-A converter. Fig.JB-2 shows the D-A control register. Fig.JB-3 shows the D-A converter equivalent circuit. Table.JB-1 Performance of D-A converter Item Conversion type Resolution Analog output pins Performance R-2R type 8 bits 2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816) D-A0 output enable bit
R-2R resistor ladder
P93/DA0
D-A register1 (8)
(Address 03DA16) D-A1 output enable bit
R-2R resistor ladder
P94/DA1
Fig.JB-1 Block diagram of D-A converter
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D-A Converter
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON Bit symbol
DA0E DA1E
Address 03DC16 Bit name
D-A0 output enable bit D-A1 output enable bit
When reset 0016 Function
0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0"
D-A register
b7 b0
Symbol DAi (i = 0,1)
Address 03D816, 03DA16 Function
When reset Indeterminate RW RW
Output value of D-A conversion
Fig.JB-2 D-A control register
D-A0 output enable bit "0" DA0 "1" 2R MSB D-A0 register0 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R
AVSS VREF
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 Do not let current flows through R-2R resistors.
Fig.JB-3 D-A converter equivalent circuit
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M16C/6K9 Group
Comparator
Comparator Circuit Comparator Configuration
A comparator circuit consists of a switch tree, ladder resistance, comparators, comparator control circuit, the comparator control register (address 03DE16), comparator data register (address 03DF16), and analog signal input pins(P50 - P57). The analog input pins (P50 - P57) are shared with the usual digital port I/O pins. The comparator control register is a 4-bit register and can generate internal analog voltages in steps of 1/16 Vcc with the contens of bits 0 to 3. In Table.JC-2 contents of bits 0 to 3 of the comparator control register and corresponding internal analog voltage generated are indicated. The compared result of the analog input voltage and internal analog voltage is stored in the comparator data register. The value of comparator control register can not be read out.
Comparator Operation
In order to perform comparator operation, first, set the port P5 direction register (address 03EB16) to "0", as P5 can be used as the analog input pins. Then write a digital value, which corresponds to the internal analog voltage to be compared, to bits 0 to 3 of the comparator control register (address 03DE16) . The voltage comparison starts immediately by the writing operation. After 28 cycles of main clock without division (the cycles needed for comparison, no relation to the frequency), the compared result of the comparator is stored in the comparator data register (address 03DF16). Each bit of this register becomes as follows depending on the status of corresponding P50 to P57 pins: When analog input voltage > internal analog voltage, it is "1". When analog input voltage < internal analog voltage, it is "0". For comparing once more, it is necessary to write data into comparator control register again even if the internal analog voltage is the same. To read the result, wait 28 cycles of main clock without division (the cycles needed for comparison, no relation to the frequency) or more after the comparator operation starts. During the 28 cycles of the comparison, the ladder resistance is turned on and the reference voltage is generated. When the comparator is not in operation, the ladder resistance is off. Therefore, unnecessary consumption is prevented. The comparison is accomplished by capacitive coupling. If the clock frequency is too low, electric charge will be lost. While the comparator is in operation, the clock frequency must be 1MHz or higher. During this time, do not execute a STP instruction, a WIT instruction, or an I/O instruction for port P5.
Data bus 8 P5 (8) P57
Compa rator
8 Comparator data register(03DF16)
b0 b3
4 Comparator control register(03DE16)
b0
R-ladder
P56
Compa rator
P50
Compa rator
Switch Tree
Comparator Comparator connection Control Cricuit signal
R-ladder connection signal VSS
Fig.JC-1 Comparator circuit
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Comparator
Table.JC-1 Correspondence of internal analog voltage and contents of bits 0 to 3 of the comparator control register. Comparator Control Register Contents of bit 0 to 3 0000 LSB 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Internal Analog Voltage 1 / 32*Vcc 1 / 16*Vcc + 1 / 32*Vcc 2 / 16*Vcc + 1 / 32*Vcc 3 / 16*Vcc + 1 / 32*Vcc 4 / 16*Vcc + 1 / 32*Vcc 5 / 16*Vcc + 1 / 32*Vcc 6 / 16*Vcc + 1 / 32*Vcc 7 / 16*Vcc + 1 / 32*Vcc 8 / 16*Vcc + 1 / 32*Vcc 9 / 16*Vcc + 1 / 32*Vcc 10 / 16*Vcc + 1 / 32*Vcc 11 / 16*Vcc + 1 / 32*Vcc 12 / 16*Vcc + 1 / 32*Vcc 13 / 16*Vcc + 1 / 32*Vcc 14 / 16*Vcc + 1 / 32*Vcc 15 / 16*Vcc + 1 / 32*Vcc
Comparator Control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CMPCON
Bit Symbol
Address 03DE16
When Reset 0016
Bit name
Internal analog voltage setting bits
Function
n/16*VCC+1/32*VCC n=setting vaule
RW
CREFS
Reserved bit Can't be written. "0" will be read out.
Fig.JC-2 Comparator control register
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PWM
PWM Output Circuit (PWM : Pulse Width Modulation)
There are 6 PWM output circuits, PWM0 to PWM5, with 8-bit resolution and operating independently. The input clock f(PC) for PWM is based on XIN, 2 division of XIN or 4 division of XIN.
Data bus
PWM0 prescaler pre-latch
PWM0 register pre-latch
Transmission control circuit
PWM0 prescaler latch f(XIN) 1/2 1/4 "00" "01" "10" Count source selection bits f(PC) PWM0 prescaler
PWM0 register latch P44 latch P44/PWM01 PWM0 register PWM0
PWM0 output pin selection bit PWM0 output enable bit P44 direction register
P93 latch P93/DA1/PWM00
PWM0 output pin selection bit PWM0 output enable bit Note: Refer to page 24 for the addresses of PWM prescaler and PWM register. P93 direction register
Fig.LA-1 PWM circuit (PWM0)
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PWM
Data Setup (PWM0)
PWM0 output pin shares with P93 or P44. PWM0 output pin is selected from either P93/PWM00 or P44/ PWM01 by bit 0 of PWM control register 0 (address 030C16). PWM0 output is enabled and starts to operate by setting bit 0 of PWM control register 1 (address 030D16) to "1" . The period of PWM is set by PWM0 prescaler (address 030016), The "H" width of output pulse is set by PWM0 register (address 030116). The following are the calculations if the prescaler value is n and PWM0 register value is m. (n = 0 to 255, m = 0 to 255) PWM period = 255 (n+1) = 31.875 (n+1) s f(XIN) (In the case of f(XIN)=8MHz, PWM counter source selection bits="002")
"H" width of output pulse = PWM period m = 0.125 (n+1) ms 255 (In the case of f(XIN)=8MHz, PWM counter source selection bits="002")
The setting of PWM1 to PWM5 are the same.
PWM Operation
By setting bit 0 ( PWM0 output enable bit) of PWM control register 1 to "1", the PWM output circuit starts to operate from default state with "H" pulse output. If the values of PWM0 register and PWM0 prescaler are modified during the PWM output operation, the corresponding pulse will be output from the next period after the modification.
31.875 m (n+1) 255 < >
s
PWM0 output < T = [31.875 (n+1)] s > m : The content of PWM0 register n : The content of PWM0 prescaler T : PWM Period ( in the case of f(XIN) = 8MHz)
Fig.LA-2 The timing of PWM period (PWM0)
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M16C/6K9 Group
PWM
A PWM0 output T The write signal to PWM0 register The write signal to PWM0 prescaler
B
C
B C = T T2
T
T2
( The modification of "H" width from "A" to "B")
( The modification of PWM period from "T" to "T2")
In the case that values of PWM0 register and PWM0 prescaler are modified, the PWM0 output will be changed from the next period after the modification.
Fig.LA-3 The PWM output timing in the case of modification of PWM register and PWM prescaler (PWM0)
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PWM
PWM control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PWMCON0
Address 030C16
When reset 0016
Bit symbol
PWMSEL0 PWMSEL1 PWMSEL2 PWMSEL3 PWMSEL4
Bit name
PWM0 output pin selection bit PWM1 output pin selection bit PWM2 output pin selection bit PWM3 output pin selection bit PWM4 output pin selection bit
Function
0 : P93/PWM00 1 : P44/PWM01 0 : P94/PWM10 1 : P45/PWM11 0 : P95/PWM20 1 : P46/PWM21 0 : P96/PWM30 1 : P47/PWM31 0 : P160/PWM40 1 : P40/PWM41 0 : P161/PWM50 1 : P41/PWM51
b7 b6
RW
PWMSEL5 PWM5 output pin selection bit
PWMCLK0 PWM count source selection bits 0 0 : f(XIN) 0 1 : f(XIN)/2 1 0 : f(XIN)/4 PWMCLK1 1 1 : Inhibit
PWM control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PWMCON1
Address 030D16
When reset 0016
Bit symbol
PWMEN0 PWMEN1 PWMEN2 PWMEN3 PWMEN4 PWMEN5
Bit name
PWM0 output enable bit PWM1 output enable bit PWM2 output enable bit PWM3 output enable bit PWM4 output enable bit PWM5 output enable bit 0 : Inhibit 1 : Enable 0 : Inhibit 1 : Enable 0 : Inhibit 1 : Enable 0 : Inhibit 1 : Enable 0 : Inhibit 1 : Enable 0 : Inhibit 1 : Enable
Function
RW
Nothing is assigned. Can not be written. The value is "0" in reading.
Fig.LA-4 PWM control registers (1)
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M16C/6K9 Group
LPC Bus Interface
LPC Bus Interface
LPC bus interface is based on Intel Low Pin Count (LPC) Interface Specification, Revision 1.0. It is I/O cycle data transfer format of serial communication. 4 channels are built in. The function of data bus buffer and data bus buffer status are almost the same as that of MELPS8-41 series. It can be written in or read out (as slave mode) by the control signals from host CPU side. The LPC bus interface functionality block diagram is shown in Figure GF-2. LPC data bus buffer functional Input / Output ports (P30-P36 ) are shared with GPIO port. The setting of bit3 (LPC bus buffer enable bit) of LPC control register ( address 02D616 ) is as below: 0: General purpose Input / Output port 1: LPC bus buffer functional Input / Output port The enabling of channel of LPC bus buffer is controlled by bits 4-7 (LPC bus buffer 0-3 enable bits) of LPC control register (address 02D616 ). The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h, 0064h. The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC 1-3 address register H, L (address 02D016 to 02D516 ). The setting value of bit2 of LPC1-3 address register (A2) L will not be decoded. The bit is "0" when read from slave CPU. The A2 status of slave address is latched to XA2 flag when written by host CPU. The input buffer full interrupt is generated when written in the data by host CPU. The Output buffer empty interrupt is generated when read out the data by host CPU. As shown in GF-1, the input buffer full interrupt request and output buffer empty interrupt request are switched by bit6, 7 of data bus buffer control register0.
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LPC Bus Interface
Input buffer full flag0 IBF0
Rising edge detection circuit
One shot pulse generator
Input Buffer Full0 interrupt request signal (IBF0 interrupt request)
Input buffer full flag1 IBF1
Rising edge detection circuit
One shot pulse generator
b7,b6 00 10 11 IBF1INT b7,b6 01 b7,b6 00 01 11 IBF2INT b7,b6 10 b7,b6 00 01 10 IBF3INT b7,b6 11 DBBCON0 bit 7,6
Input Buffer Full1/output buffer empty interrupt request signal (IBF1/OBE interrupt request)
Input buffer full flag2 IBF2
Rising edge detection circuit
One shot pulse generator
Input Buffer Full2/output buffer empty interrupt request signal (IBF2/OBE interrupt request)
Input buffer full flag3 IBF3
Rising edge detection circuit
One shot pulse generator
Input Buffer Full3/output buffer empty interrupt request signal (IBF3/OBE interrupt request)
Output buffer full flag0 OBF0
OBE0
Rising edge detection circuit Rising edge detection circuit Rising edge detection circuit Rising edge detection circuit
One shot pulse generator OBE One shot pulse generator One shot pulse generator One shot pulse generator
OBE1 Output buffer full flag1 OBF1 OBE2
Output buffer full flag2 OBF2
Output buffer full flag3 OBF3
OBE3
IBF0 IBF0 interrupt request
IBF1 IBF1INT IBF2 IBF2INT IBF3 IBF3INT
OBF0(OBE0) OBF1(OBE1) OBF2(OBE2) OBF3(OBE3) OBE
(Example) Data bus buffer control register 0 bit 7=1, bit 6=1 IBF1/OBE interrupt request IBF2/OBE interrupt request IBF3/OBE interrupt request
Fig.GF-1 Interrupt, request, circuit of Data Bus Buffer
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M16C/6K9 Group
LPC Bus Interface
P34/LFRAME P35/LRESET P36/LCLK
Address register HH (Note1)
Address register HL (Note1)
Address register LH (Note1)
Input Data Comparator
P30/LAD0
P31/LAD1 Input Control Circuit
Address register LL (Note1)
RD/WR register
Start register
P32/LAD2
Input Data Buffer [7:4] Input Data Buffer [3:0]
Output Data Buffer [7:4]Output Data Buffer [3:0]
P33/LAD3 Data bus buffer status register U7 U6 U5 U4 XA2 U2 IBF OBF
Output Control Circuit
SYNC register
TAR register
Interrupt generate Circuit
Interrupt signal IBF, OBE
b7
b6
b5
b4
b3
b2
0
0
LPC control register (address 02D616)
Note1 : LPC bus interface channel 0 is fixed on slave address "0060h", "0064h".
Fig.GF-2 LPC bus interface function block diagram (LPC1)
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Internal Data Bus
System Bus
M16C/6K9 Group
LPC Bus Interface
Figure GF-3 Shows Data bus buffer control registers Figure GF-4 Shows Data bus buffer status register Figure GF-5, 6 Shows LPC related registers
Data bus buffer status register (DBBSTS0-DBBSTS3)
This is 8-bit register. The bit 0, 1, 3 are read only bits and indicate the status of data bus buffer. Bit 2, 4, 5, 6, 7 are user definable and flags which can be read and written by software. The data bus buffer status register can be read out by host CPU when the slave address (16 bit) bit2 (A2) is high. * Output buffer full flag (OBF) The bit will be set to "1" when a data is written into output data bus buffer and will be cleared to "0" when host CPU read out the data from output data bus buffer. * Input buffer full flag (IBF) The bit will be set to "1" while a data is written into input data bus buffer by host CPU and will be cleared to "0"when the data is read out from input data bus buffer by slave CPU. * XA2 flag (XA2) The bit 2 of slave address (16 bits) is latched while a data is written into data bus buffer.
Input data bus buffer register (DBBIN0-DBBIN3)
When there is a write request from host CPU, the data on the data bus will be latched to DBBIN0-3. The data of DBBIN0-3 can be read out from data bus buffer registers (Address:02C016, 02C216 , 02C416 , 02C616 ) in SFR field.
Output data bus buffer register (DBBOUT0-DBBOUT3)
When writing data to data bus buffer registers (Address: 02C016 , 02C216 , 02C416 , 02C616 ), the data will be transferred to DBBOUT0-3 automatically. The data of DBBOUT0-3 will be output to the data bus when there is a read request from host CPU and the status of bit2 (A2) of slave address (16 bits) is low.
LPCi address register H/L (LPC1ADH-LPC3ADH / LPC1ADL-LPC3ADL)
The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h, 0064h. The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC1-3 address registers H/L (02D016 to 02D516 ). The settings are for slave address upper 8 bits and lower 8 bits. And these registers can be set and cleared in any time. The bit 2 of LPC 1-3 address L is not decoded regardless of the setting value. When slave CPU reads LPC13 address registers, the bit2 (A2) of address low byte will be fixed to "0". The bit2 (A2) status of slave address is latched to XA2 flag when written by host CPU. The slave addresses that are already set in these registers will be used for comparing with the addresses to be received.
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LPC Bus Interface
Data bus buffer control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DBBCON0
Address 02C816
When reset 000000002
Bit symbol
Bit name
Function
RW
Nothing is assigned. Cannot be written. The value is "0" in reading. IBFSEL IBF/OBE interrupt request select bit
b7 b6
0 0 1 1
0 1 0 1
(Note 1) : OBE disable : OBE enable, IBF1 disable : OBE enable, IBF2 disable : OBE enable, IBF3 disable
Note 1: By setting these two bits, one of IBF1 to IBF3 interrupt requests will be switched to OBE interrupt request. There is no relative between IBF0 interrupt request and these two bits. 0,0 IBF0 IBF1 IBF2 IBF3 0,1 IBF0 OBE IBF2 IBF3 1,0 IBF0 IBF1 OBE IBF3 1,1 IBF0 IBF1 IBF2 OBE
Interrupt
b7, b6
IBF0 interrupt IBF1 interrupt IBF2 interrupt IBF3 interrupt
Data bus buffer control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DBBCON1
Address 02C916
When reset 000000002
Bit symbol
OBF0SEL OBF00EN OBF01EN OBF1EN OBF2EN OBF3EN
Bit name
OBF0 output selection bit OBF00 output enable bit OBF01 output enable bit OBF1 output enable bit OBF2 output enable bit OBF3 output enable bit
Function
0 : OBF00 enable 1 : OBF01 enable 0 : P40 as GPIO 1 : P40 as OBF00 output 0 : P43 as GPIO 1 : P43 as OBF01 output 0 : P44 as GPIO 1 : P44 as OBF1 output 0 : P45 as GPIO 1 : P45 as OBF2 output 0 : P46 as GPIO 1 : P46 as OBF3 output
RW
Nothing is assigned. Cannot be written. The value is "0" in reading.
Fig.GF-3 Data bus buffer control registers
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M16C/6K9 Group
LPC Bus Interface
Data bus buffer status register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DBBSTS0 DBBSTS1 DBBSTS2 DBBSTS3
Address 02C116 02C316 02C516 02C716
When reset 000000002 000000002 000000002 000000002
Bit symbol
OBF IBF U2 XA2
Bit name
Output buffer full flag Input buffer full flag User definable flag XA2 flag
Function
0 : Buffer empty 1 : Buffer full 0 : Buffer empty 1 : Buffer full This flag can be freely defined by user This flag is indication the A2 status of the 16 bit slave address when IBF flag is set This flag can be freely defined by user
RW
U4 U5 U6 U7
User definable flag
Fig.GF-4 Data bus buffer status register
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LPC Bus Interface
LPCi address register L (i=1,2,3)
b7 b6 b5 b4 b3 b2 b1 b0
(Note2) Address 02D016 02D216 02D416 When reset 000000002 000000002 000000002 RW
Symbol LPC1ADL LPC2ADL LPC3ADL
Bit symbol
LPCSAD0 LPCSAD1 LPCSAD2 LPCSAD3 LPCSAD4 LPCSAD5 LPCSAD6 LPCSAD7
Bit name
Slave address0 Slave address1 Slave address2 (Note1) Slave address3 Slave address4 Slave address5 Slave address6 Slave address7
Note1: Always returns "0" when read, even if writing "1" to this bit. Note2: Do not set the same 16 bits slave address in each channel.
LPCi address register H (i=1,2,3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LPC1ADH LPC2ADH LPC3ADH
Address 02D116 02D316 02D516
When reset 000000002 000000002 000000002 RW
Bit symbol
LPCSAD8 LPCSAD9 LPCSAD10 LPCSAD11 LPCSAD12 LPCSAD13 LPCSAD14 LPCSAD15
Bit name
Slave address8 Slave address9 Slave address10 Slave address11 Slave address12 Slave address13 Slave address14 Slave address15
Fig.GF-5 LPC related registers
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M16C/6K9 Group
LPC Bus Interface
LPC control register (LPCCON)
* LPC bus interface enable bit (LPCBEN) "0": P30 -P36 use as GPIO "1": P30 -P36 use as LPC bus interface * LPC bus buffer 0 enable bit (LPCEN0) "0": LPC bus buffer0 disable "1": LPC bus buffer0 enable * LPC bus buffer 1 enable bit (LPCEN1) "0": LPC bus buffer1 disable "1": LPC bus buffer1 enable * LPC bus buffer 2 enable bit (LPCEN2) "0": LPC bus buffer2 disable "1": LPC bus buffer2 enable * LPC bus buffer 3 enable bit (LPCEN3) "0": LPC bus buffer3 disable "1": LPC bus buffer3 enable * LPC software reset bit (LPCSR)
______________
By setting the bit to "1", LPC interface is reset by the same status as LRESET="L". After 1.5 cycles of BCLK at writing "1", reset is released and the bit becomes "0". Nothing happens if "0" is set. * SYNC output selection bits (SYNCSEL0,SYNCSEL1) The content of SYNC output can be selected by bit 0,1 (SYNC output selection bits) of LPC control register. Fig.GF-6 shows the configuration of LPC control register, Table.GF-1 shows the content of SYNC output selected by SYNC output selection bits. Table GF-1 SYNC output SYNCSEL1 0 0 1 1 SYNCSEL0 0 1 0 1 SYNC cycle 1 4 1 4 1st cycle 00002 01102 10102 01102 SYNC output 2nd cycle 3rd cycle 01102 01102 01102 01102 4th cycle 00002 10102
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LPC Bus Interface
LPC control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LPCCON Bit symbol SYNCSEL0 SYNCSEL1 LPCSR LPCBEN LPCEN0 LPCEN1 LPCEN2 LPCEN3
Address 02D616 Bit name
b1 b0
When reset 000000002 Function 0 0: OK 0 1: Long & OK 1 0: Err 1 1: Long & Err 0 : The release of reset (Note) 1 : Reset 0 : P30 - P36 as GPIO 1 : LPC bus buffer enable 0 : LPC bus buffer 0 disable 1 : LPC bus buffer 0 enable 0 : LPC bus buffer 1 disable 1 : LPC bus buffer 1 enable 0 : LPC bus buffer 2 disable 1 : LPC bus buffer 2 enable 0 : LPC bus buffer 3 disable 1 : LPC bus buffer 3 enable RW
SYNC output selection bits
LPC software reset bit LPC interface enable bit LPC bus buffer 0 enable bit LPC bus buffer 1 enable bit LPC bus buffer 2 enable bit LPC bus buffer 3 enable bit
Note: For LPC software reset, the bit will automatically return to "0" after writing "1".
Fig.GF-6 LPC control register
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LPC Bus Interface
Basic operation of LPC bus interface
The status transition of LPC bus interface is shown in Figure GF-7. Setting steps for using LPC bus interface is explained below. * Setting bit3 (LPC interface enable bit) of LPC control register ( address 02D616 ) to "1" * Choosing which LPC bus buffer channel will be used * Setting "1" to bits 4-7 (LPC bus buffer 0-3 enable bit) of LPC control register ( address 02D616 ). * The 16-bit slave address of LPC bus buffer channel is defined by writing 16-bit slave address to LPC 1-3 address registers ( address 02D016 to 02D516 ). If channel 1-3 LPC bus buffer is chosen, set the address to the corresponding address register. * Selecting IBF/ OBE interrupt in data bus buffer control register0 ( address 02C816 ) * Selecting OBF output port in data bus buffer control register1 ( address 02C916 ) <1> Example of I/O writing cycle from HOST Writing timing is shown in Figure GF-8. The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the
_______________
rising edge of LCLK. Communication will start from LFRAME falling edge. ______________ * 1st cycle : When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start frame detecting. _______________ * 2nd cycle : When LFRAME is "High", sending "001X2 " to LAD[3:0] for write frame detecting. * From 3rd cycle to 6th cycle: These four cycles are detecting for 16 bits slave address. 3rd cycle: The slave address which is from host is written to slave address register [15:12] through LAD[3:0] 4th cycle: The slave address which is from host is written to slave address register [11:8] through LAD[3:0] 5th cycle: The slave address which is from host is written to slave address register [7:4] through LAD[3:0] 6th cycle: The slave address which is from host is written to slave address register [3:0] through LAD[3:0] * 7th and 8th cycles are used for one data byte transfer. 7th cycle: The data which is from host is written to input data buffer[3:0] through LAD[3:0] 8th cycle: The data which is from host is written to input data buffer[7:4] through LAD[3:0] * 9th and 10thcycles are for changing the communication direction from hostslave to slavehost 9th cycle: Host outputs "11112 " to LAD[3:0] 10thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction. * 11th cycle: The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge. * 12th cycle: The "11112 " is output to LAD[3:0]. The XA2 and IBF flag are set. IBF interrupt signal is generated. * 13th cycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction. During the host write period, the bit2 (A2) status of 16 bits slave address will be latched to XA2 flag. When 8 bits data from input data buffer are read out by slave CPU, the IBF flag will be cleared simultaneously.
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LPC Bus Interface
<2> Example for I/O reading cycle from HOST Reading timing is shown in Figure GF-9. The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the _______________ rising edge of LCLK. Communication will start from LFRAME falling edge. _______________ * 1st cycle: When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start detecting. _______________ * 2ndcycle: When LFRAME is "High", the host send "000X2 " on LAD[3:0] to inform the cycle type as I/O read. * From 3rd cycle to 6thcycle: These four cycles are detecting for 16 bits slave address. 3rdcycle: The slave address which is from host is written to slave address register [15:12] throughLAD[3:0] 4thcycle: The slave address which is from host is written to slave address register [11:8] throughLAD[3:0] 5thcycle: The slave address which is from host is written to slave address register [7:4] throughLAD[3:0] 6thcycle: The slave address which is from host is written to slave address register [3:0] throughLAD[3:0] * 7th and 8thcycles are used for changing the communication direction from hostslave to slavehost 7thcycle: Host is output "11112 " to LAD[3:0] 8thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction. * 9thcycle : The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge. * 10th and 11thcycles are for output 8 bits data from output data buffer or output 8 bits data from status register. 10thcycle: Sending output data buffer [3:0] to LAD[3:0] or sending data of status register [3:0] to LAD[3:0] 11thcycle: Sending output data buffer [7:4] to LAD[3:0] or sending data of status register [7:4] to LAD[3:0]. * 12thcycle: The "11112 " is output to LAD[3:0]. The OBF flag is cleared and OBE interrupt signal is generated. * 13thcycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction. OBF flag will be set when 8 bits data are written to output data buffer by slave CPU.
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LPC Bus Interface
Data WR (I/O write cycle)
START WR 16 BIT ADDRESS DATA TAR SYNC TAR
LCLK
LFRAME (Note1) LAD [3:0]
Input buffer
XA2 flag
IBF flag Driven by the HOST Driven by the SLAVE
Command WR (I/O write cycle)
START WR 16 BIT ADDRESS DATA TAR SYNC TAR
LCLK
LFRAME (Note1) LAD [3:0]
Input buffer
XA2 flag
IBF flag Driven by the HOST Driven by the SLAVE
Note1 : LAD0 to LAD3 pins remain Hi-Z after transfer completion
Fig.GF-7 Data and Command write timing figure
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LPC Bus Interface
Data RD (I/O read cycle)
START RD 16 BIT ADDRESS TAR SYNC DATA TAR
LCLK
LFRAME (Note1) LAD [3:0]
OBF flag Driven by the HOST Driven by the SLAVE
Status RD (I/O read cycle)
START RD 16 BIT ADDRESS TAR SYNC DATA TAR
LCLK
LFRAME (Note1) LAD [3:0]
OBF flag
(Note2)
Driven by the HOST
Driven by the SLAVE
Note1 : LAD0 to LAD3 pins become Hi-Z after transfer completion. Note2 : OBF flag does not change.
Fig.GF-8 Data and Status read timing figure
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HOSTEN
Table GF-2 Function explanation of the control input and output pins in LPC bus interface function
M16C/6K9 Group
Pin name Function
02C916 Bit 1 02C916 Bit 2 02C916 Bit 3 02C916 Bit 4 02C916 Bit 5 02C916 Bit 6
Name
LPC interface enable bit OBF00 OBF01 output output enable bit enable bit OBF3 output enable bit control bit OBF1 OBF2 output output enable bit enable bit
OBF0 output enable bit
02D616 Bit 3
02C916 Bit 0
Input/ Output
Jun 06, 2003
P30/LAD0
LAD0
1
I/O I/O I/O I/O I I I
1 0
It is used for indicating the start of LPC cycle and termination of abnormal communication cycle. LPC reset signal. LPC bus interface function is reset. LPC synchronous clock signal. Status output signal. OBF00 output. Status output signal. OBF01 output. Status output signal. OBF1 output.
P31/LAD1
LAD1
1
LPC bus used for transmitting and receiving address, command and data between Host CPU and peripheral devices.
P32/LAD2
LAD2
1
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LPC Bus Interface
P33/LAD3
LAD3
1
P34/LFRAME LFRAME
1
P35/LRESET
LRESET
1
P36/LCLK
LCLK
1
P40/OBF00
OBF00
0
O O
1 1 1
P43/OBF01
OBF01
1 0 1
P44/OBF1
OBF1
O O O
P45/OBF2
OBF2
Status output signal. OBF2 output. Status output signal. OBF3 output.
P46/OBF3
OBF3
M16C/6K9 Group
LPC Bus Interface
______________
Table GF-3 Conditions of LPC bus interface function induced by LRESET input
______________ ______________
Pin name / Internal register P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3
_________________
LRESET="H" LPC bus interface function(function is select) I/O port
LRESET="L"
Note
Pin
P34/LFRAME _______________ P35/LRESET P36/LCLK P40/OBF00 P43/OBF01 P44/OBF1 P45/OBF2 P46/OBF3 P42/GateA20 Input data bus buffer Output data bus buffer U flag 7,6,5,4,2 XA2 flag
I/O port LPC bus interface function I/O port OBF output is enable until LRESET="L". A spike pulse may be output to the port when the port is already set to L output port and OBF signal is output to the port ______________ just before LRESET is set to L.
______________
unstable It can't be written by slave side. It can be written and read by Initialization to "0" only for slave side. Initialization to "0" Initialization to "0" Initialization to "0" It can be written and read by slave side. It can be written and read by slave side. Initialization DBBSTS0. There is possibility to generate IBF interrupt request. There is possibility to generate OBE interrupt request.
Internal register
IBF flag OBF flag LPCADH/L LPCCON GA20 circuit
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LPC Bus Interface
GateA20 output function
The GateA20 pin (port P42) can be controlled by LPC interface function channel 0 in hardware. Hardware GateA20 is sharing with P42 pin. Setting "1" to bit 0 of GateA20 control register enables the hardware GateA20 function. The default value of hardware GateA20 is "1". The GateA20 control register is shown in Fig.GF-9. When the host CPU writes "D1" command to address 006416, and then writes data to address 006016 in succession, the value of bit 1 of the data will be output to GateA20 pin. The timing is shown in Fig.GF-10. The GateA20 operation sequences are shown in Fig.GF-11, Fig.GF-12. As shown in the figures, there is no change in input buffer full flag(IBF0) and no input buffer full(IBF) interrupt request, but the input data bus buffer and XA2 flag are changed in these sequences. The value of the GateA20 output pin will be held till the data next to D1 command is written in. P42 becomes _____________ I/O port and the the value of GateA20 becomes "0" when LRESET input is "L". GateA20 will be initialized even if the sequence is executed. However, the GateA20 enable bit will not be changed and GateA20 output pin _____________ will be resumed after the LRESET input becomes "H".
GateA20 control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol GA20CON
Address 002CA16
Reset 0016
Bit Symbol
GA20EN
Bit name
GateA20 enable bit
Function
0 : P42 as GPIO 1 : Hardware GateA20 function enable Must be set to "0"
RW
Reserved bit
Nothing is assigned. Meaningless in writing. "0" in reading.
Fig.GF-9 GateA20 control register
START
WRITE
16-bit address
DATA
TAR
SYNC
TAR
LCLK
LFRAME
LAD (3:0)
GateA20 pin
Previous value
The value of bit 1 of the data
Fig.GF-10 GateA20 output timing
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LPC Bus Interface
Sequence 1 (basic operation 1)
LPC communication GateA20 pin IBF0 flag refresh IBF interrupt request
Write D1 to 006416 Write data to 006016 Write FF to 006416
Previous value No No No No
Bit 1 value of the data No No
Sequence 2 (basic operation 2)
LPC communication GateA20 pin IBF0 flag refresh IBF interrupt request
Write D1 to 006416 Write data to 006016
Write data other than FF and D1 to 006416
Previous value No No No No
Bit 1 value of the data Yes Yes
Sequence 3 (basic operation 3)
LPC communication GateA20 pin IBF0 flag refresh IBF interrupt request
Write D1 to 006416 Write data to 006016 Write data to 006016
Previous value No No No No
Bit 1 value of the data Yes Yes
Fig.GF-11 GateA20 operation sequence (1)
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LPC Bus Interface
Sequence 4 (re-trigger)
LPC communication GateA20 pin IBF0 flag refresh IBF interrupt request
Write D1 to 006416 Write D1 to 006416 Write data to 006016
Previous value No No No No No
Bit 1 value of the data
No
Sequence 5 (cancel operation)
LPC communication
Write D1 to 006416
Write data other than D1 to 006416
GateA20 pin IBF0 flag refresh IBF interrupt request
Previous value No No Yes Yes
Sequence 6 (continuance operation)
LPC communication
Write D1 to 006416 Write data1 to 006016 Write D1 to 006416 Write data2 to 006016
GateA20 pin IBF0 flag refresh IBF interrupt request
Previous value No No No No
Bit 1 value of the data No No No No
The value of bit 1 of data 2
Fig.GF-12 GateA20 operation sequence (2)
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Serial Interrupt Output
Serial Interrupt Output
The serial interrupt output is the circuit that outputs the interrupt request to the host with serial interrupt data format. Tab.SI-1 shows the specification of serial interrupt output. Table.SI-1 Specifications of serial interrupt output
Item The factors of serial interrupt Specification The numbers of serial interrupt requests (numbers of channels) that can output simultaneously are 5 factors. Each interrupt factor of each channel is explained as follows. * Channel 0 By setting "1" to IRQi request bit (bit 5, 6 i=1,12) of IRQ request register 0, the interrupt request can be generated. Synchronized with OBF00 and OBF01 that are the host bus interface internal signals, the serial interrupt request can be generated. * Channel 1-3 By setting "1" to IRQ request bit (bit 5) of IRQ request register 1-3, the interrupt request can be generated. Synchronized with OBF1-3 that are the host bus interface internal signals, the serial interrupt request can be generated. * Channel 4 By setting "1" to IRQ request bit (bit 5) of IRQ request register 4, the interrupt request can be generated. * Channel 0 Setting the IRQ1 request bit (bit 5) of IRQ request register0 to "1" or detecting OBF00, which is the host bus interface internal signal, selects Frame 1. Setting the IRQ12 request bit (bit 6) of IRQ request register0 to "1" or detecting OBF01, which is the host bus interface internal signal, selects Frame 12. * Channel 1-4 Selecting the frame select bit (bit 0-4) of IRQ request register1-4 selects Frame 1-15 or extend Frame 0-10. The operation synchronized with LCLK (Max. 33MHz). (Note) Setting the clock restart enable bit (bit 6) of serial interrupt control register0 to "1" requests the clock restart if the clock has stopped or slowed down in serial interrupt output. Setting the clock stop inhibition bit (bit 5) of serial interrupt control register0 to "1" requests the inhibition of clock stop if the clock tends to stop or slow down in serial interrupt output. Setting the OBF00, OBF01, OBF1-3 sync enable bit (bit 0-4) of serial interrupt control register0 to "1" enables the OBF synchronization.
The number of frame
Operation clock Clock restart
Clock stop inhibition
OBF sync enable
Note: To enable LCLK, it is necessary to enable the LPC bus interface function.
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Serial Interrupt Output
internal data bus Serial interrupt control register0 (address:02B016 ) IRQ request register0 (address:02B216 ) IRQ request register1 - 4 (address:02B316 , 02B416, 02B516 ,02B616) b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Clock stop inhibiting enable Clock restart enable
IRQ request 00,01
IRQ request 1 - 4
OBF sync enable Serial interrupt enable Internal signals OBF00,OBF01, OBF1 - OBF3 Serial interrupt request Control circuit IRQ request 0 - 4 IRQ frame number 1 - 4
Port control section
IRQ request 0-4
IRQ request clear
Frame number (CH0 - CH4)
SERIRQ
Serial interrupt output Control circuit
Clock operation Status & finish acknowledge
Clock restart request & start frame start request
Clock monitor/ Control circuit
CLKRUN LCLK Reset selection LRESET b7 b6 b5 b4 b3 b2 b1 b0 PRST Serial interrupt control register1(address: 02B116 ) f1 Internal data bus
Fig.SI-1 Serial interrupt block chart
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Serial Interrupt Output
(1) Register explanation
Fig.SI-2 shows the configuration of IRQ request register0, Fig.SI-3 shows the configuration of IRQ request register1-4, Fig.SI-4, SI-5 show the configurations of serial interrupt control register0,1 respectively.
q IRQ request register0 IRQR0
The serial interrupt request of Channel 0 is set by software.
*IRQ1 request bit IR0
Setting the bit to "1" generates the serial interrupt request (Frame 1). By setting the OBF00 sync enable bit (bit 0) of the serial interrupt control register0 to "1", the value of IR0 is the same as that of OBF00, which is the host bus interface internal signal. When the internal signal OBF00 is "1", the serial interrupt is generated. IR0 is cleared to "0" by writing "0" in software. IR0 can not be cleared to "0" by software when the internal signal OBF00 is "1" if OBF00 sync enable bit is set to "1".
*IRQ12 request bit IR1
Setting the bit to "1" generates the serial interrupt request (Frame 12). By setting the OBF01 sync enable bit (bit 1) of the serial interrupt control register0 to "1", the value of IR1 is the same with that of OBF01, which is the host bus interface internal signal. When the internal signal OBF01 is "1", the serial interrupt is generated. IR1 is cleared to "0" by writing "0" in software. IR1 can not be cleared to "0" by software when the internal signal OBF01 is "1" if OBF01 sync enable bit is set to "1".
IRQ request register0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol: IRQR0 Bit symbol
Address: 02B216
When reset: 0016 Function
RW
Bit name Nothing is assigned. Meaningless in writing, "0" in reading. IR0 IR1 IRQ1 request bit IRQ12 request bit
0: No IRQ1 request 1: IRQ1 request 0: No IRQ12 request 1: IRQ12 request
Nothing is assigned. Meaningless in writing, "0" in reading.
Fig.SI-2 Configuration of IRQ request register0
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Serial Interrupt Output
q IRQ request register i IRQRi (i=1-4)
The serial interrupt request of Channel 1-4 is set by software, or asserting frame is selected.
*IRQ request bit IR
Setting the bit to "1" generates the serial interrupt request. By setting the OBFj sync enable bit (bit2-4, j=1-3) of the serial interrupt control register0 to "1", the value of IR is the same as that of OBFj, which is the host bus interface internal signal. When the internal signal OBFj is "1", the serial interrupt is generated. IR is cleared to "0" by writing "0" in software. IR can not be cleared to "0" by software when the internal signal OBFj is "1" if OBFj sync enable bit is set to "1".
q IRQ select bit IS0-4
The asserting frame is selected.
IRQ request register1-4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IRQR1 IRQR2 IRQR3 IRQR4
Bit symbol IS0
Address 02B316 02B416 02B516 02B616
Bit name
When reset 0016 0016 0016 0016
Function IRQ Frame 0 0 0 0 0 : No SERIRQ output 0 0 0 0 1 : Frame 1 0 0 0 1 0 : Frame 2 0 0 0 1 1 : Frame 3 0 0 1 0 0 : Frame 4 0 0 1 0 1 : Frame 5 0 0 1 1 0 : Frame 6 0 0 1 1 1 : Frame 7 0 1 0 0 0 : Frame 8 0 1 0 0 1 : Frame 9 0 1 0 1 0 : Frame 10 0 1 0 1 1 : Frame 11 0 1 1 0 0 : Frame 12 0 1 1 0 1 : Frame 13 0 1 1 1 0 : Frame 14 0 1 1 1 1 : Frame 15 1 0 0 0 0 : Can't select 1 0 0 0 1 : Can't select 1 0 0 1 0 : Can't select 1 0 0 1 1 : Can't select 1 0 1 0 0 : Can't select 1 0 1 0 1 : Extend Frame 0 1 0 1 1 0 : Extend Frame 1 1 0 1 1 1 : Extend Frame 2 1 1 0 0 0 : Extend Frame 3 1 1 0 0 1 : Extend Frame 4 1 1 0 1 0 : Extend Frame 5 1 1 0 1 1 : Extend Frame 6 1 1 1 0 0 : Extend Frame 7 1 1 1 0 1 : Extend Frame 8 1 1 1 1 0 : Extend Frame 9 1 1 1 1 1 : Extend Frame 10
b4b3b2b1b0
RW
Frame select bit
IS1
IS2
IS3
IS4
IR
IRQ request bit
0: No IRQ request 1: IRQ request
Nothing is assigned. Meaningless in writing, "0" in reading.
Fig.SI-3 Configuration of IRQ request register1-4
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Serial Interrupt Output
q Serial interrupt control register0 SERCON0
The operation condition of serial interrupt is set.
*OBFi sync enable bit SENi (i=00,01,1-3)
By setting the bit to "1", sync with the OBFi of host interface, the serialized interrupt can be generated.
*Clock stop inhibition bit SUPEN
Setting the bit to "1" will request the inhibition of clock if the clock tends to stop or slow down in serial interrupt request.
*Clock restart enable bit RUNEN
Setting the bit to "1" requests the clock restart during the clock stop or clock slow down in serial interrupt request.
*Serial interrupt enable bit IRQEN
__________ _______________
0: SERIRQ, PRST, CLKRUN are I/O ports. __________ _______________ 1: SERIRQ, PRST, CLKRUN are serial interrupt function ports.
Serial interrupt control register0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SERCON0 Bit symbol SEN00 SEN01 SEN1 SEN2 SEN3 SUPEN RUNEN IRQEN
(Note 1)
Address 02B016 Bit name
When reset 0016 Function 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Stop control operation 1: No stop control operation 0: No clock restart 1: Clock restart 0: Serial interrupt inhibition 1: Serial interrupt enable
_______________
RW
OBF00 sync enable bit OBF01 sync enable bit OBF1 sync enable bit OBF2 sync enable bit OBF3 sync enable bit Clock stop inhibition bit Clock restart enable bit Serial interrupt enable bit
Note 1 : When IRQEN is set to "1", if either SUPEN or RUNEN is set to "1", P46 will function as CLKRUN I/O and the output type is N channel open drain.
__________ __________
Note 2 : When the bit is set to "1", P43, P45 function as SERIRQ, PRST respectively. Even the bit is set to "1", P45/PRST can function as GPIO if bit 1 of serial interrupt control register 1 (address 02B116) is set to "1".
Fig.SI-4 Configuration of serial interrupt control register0
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Serial Interrupt Output
q Serial interrupt control register1 SERCON1
The register is for setting the pins of serial interrupt.
*Reset selection bit RSEL
__________
0: The input of PRST is the reset signal. ______________ 1: The input of LRESET is the reset signal. (Note1) __________ Note 1: The PRST pin becomes I/O port if setting the bit to "1".
Serial interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
00
0
0
Symbol SERCON1 Bit symbol Reserved bit RSEL Reserved bit
Address 02B116 Bit name
When reset 0016 Function Must be "0". RW
Reset selection bit
0 : Select PRST pin. 1 : Select LRESET pin. Must be "0". 0 : OBF00 and OBF01 are independent. 1 : OBF00 and OBF01 are merged (logical OR). 0: Normal operation 1: SEN00, SEN01 is cleared when OBF0 is cleared. Must be "0".
OBF0MRG
OBF0 mergence bit
OBF0CLR
OBF0 cut sync bit
Reserved bit Nothing is assigned. Meaningless in writing. "0" in reading.
Fig.SI-5 Configuration of serial interrupt control register1
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Serial Interrupt Output
*OBF0 mergence function
By setting the bit to "1", the signal, which is logically OR by OBF00 and OBF01 signals from LPC bus interface, will output to IRQ1 and IRQ12 of serial interrupt circuit. With the function, the IRQ1 and IRQ12 request bits can be cleared simultaneously by H/W at the read of output data buffer from system if both IRQ1 and IRQ12 request bits are set in the case that IRQ1 request bit (or IRQ12 request bit) is set after that of IRQ12 (or IRQ1) because of the overwrite to the output data buffer.
*OBF0 sync inhabitant function
By setting bit 4 of serial interrupt control register 1 (OBF cut sync bit), simultaneously after the read of OBF0, the OBF0 sync function can be inhabited. If the bit is set to "1", simultaneously after the clear of OBF00 or OBF01, SEN00 (OBF00 sync enable bit) and SEN01 (OBF01 sync enable bit) bits are cleared (sync inhabitation) by H/W. The configuration of serial interrupt control register 1 and the switching circuit controlled by OBF0MRG, OBF0CLR are shown in Fig. SI-5, Fig. SI-6 respectively.
OBF0CLR OBF0MRG OBF0 OBF0
"0"
RD RD/WR
OBF0001
SEN00 To IRQ1 request bit of serial interrupt circuit WR IR0
"1"
OBF0 clear signal (Triggered by host read)
"0"
RD/WR
OBF0001
SEN01 To IRQ12 request bit of serial interrupt circuit WR IR0 RD
OBF0SEL
"1"
Fig.SI-6 The switching circuit controlled by OBF0MRG, OBF0CLR
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Serial Interrupt Output
q Serial interrupt control register2 SERCON2
The polarity of serial interrupt output can be selected by bit 0 to bit 5 of serial interrupt control register 2.
When the bit is set to "0": If there is a request, Hiz-Hiz-Hiz If there is no request, L-H-Hiz When the bit is set to "1": If there is a request, L-H-Hiz If there is no request, Hiz-Hiz-Hiz Only the default value of bit 4 (serial interrupt polarity bit 3) of serial interrupt control register 2 after reset is "1". Fig.SI-7 shows the configuration of serial interrupt control register 2.
Serial interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SERCON2 Bit symbol SERSEL00
Address 02B716 Bit name
When reset 1016 Function Select serial interrupt output polarity of IRQ1 in channel 0. (Note) Select serial interrupt output polarity of IRQ12 in channel 0. (Note) Select serial interrupt output polarity of IRQ in channel 1. (Note) Select serial interrupt output polarity of IRQ in channel 2. (Note) Select serial interrupt output polarity of IRQ in channel 3. (Note) Select serial interrupt output polarity of IRQ in channel 4. (Note) RW
Serial interrupt polarity selection bit 00 Serial interrupt polarity selection bit 01 Serial interrupt polarity selection bit 1 Serial interrupt polarity selection bit 2 Serial interrupt polarity selection bit 3 Serial interrupt polarity selection bit 4
SERSEL01
SERSEL1
SERSEL2
SERSEL3
SERSEL4
Nothing is assigned. Meaningless in writing. "0" in reading. Note: "0" "1" : If there is a request If there is no request : If there is a request If there is no request Hiz-Hiz-Hiz L-H-Hiz L-H-Hiz Hiz-Hiz-Hiz
Fig.SI-7 The configuration of serial interrupt control register 2
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M16C/6K9 Group
Serial Interrupt Output
(2) The operation of serial interrupt
A cycle operation of serial interrupt starts with start frame and finishes with stop frame. There are 2 kinds of operation mode: continuous mode and quiet mode. The next operation mode is judged by monitoring the length of stop frame sent from host side.
q The timing of serial interrupt cycle
Fig.SI-8 shows an example of basic timing of serial interrupt cycle. Start frame The start frame will be detected if the SERIRQ remains "L" in 4-8 clock cycles. IRQ data frame Each IRQ data frame is 3 clock cycles. *Channel 0-2,4:If the IRQ request bit is "0", then the SERIRQ is driven to "L" during the 1st clock cycle of the corresponding data frame, to "H" during the 2nd clock cycle, to high impedance during the 3rd clock cycle. If the IRQ request bit is "1", then the SERIRQ is high impedance during all of the 3 clock cycles. *Channel 3:If the IRQ request bit is "0", then the SERIRQ is high impedance during all of the 3 clock cycles. If the IRQ request bit is "1", then the SERIRQ is driven to "L" during the 1st clock cycle of the corresponding data frame, to "H" during the 2nd clock cycle, to high impedance during the 3rd clock cycle. zStop frame The stop frame will be detected if the SERIRQ remains "L" in 2 or 3 clock cycles. The next operation mode is quiet mode if the length of "L" is 2 clock cycles, the continuous mode if the length is 3 clock cycles.
Start frame Clock SERIRQ Driver source System side
frame 0
frame 1
frame 15
IOCHK
Stop frame
to the next cycle
Device side
Device side
System side
Fig.SI-8 Basic timing of serial interrupt cycle
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Serial Interrupt Output
q Operation mode
Fig.SI-9 shows an example of timing of continuous mode, Fig.SI-10 shows that of quiet mode. Continuous mode __________ _______________ After reset, at the rising edge of PRST (or LRESET) or the length of the last stop frame of serial interrupt cycle being 3 clock cycles, it will be the continuous mode. After receiving the start frame (Note 1), the Frame 1, Frame 12 or frames selected in each channel will be asserted. Note 1: If the length of "L" is less than 4 clock cycles or more than 9 clock cycles, the start frame will not be detected and the next start (the falling edge of SERIRQ) is waited.
Start frame (Note1) Clock SERIRQ line System*SERIRQ output Device*SERIRQ output Driver source System side Device side IRQ0 frame IRQ1 frame IRQ2 frame IRQ3 frame
Note1 . The start frame is set to 4 clock as setting exemple
Fig.SI-9 Timing diagram of continuous mode
Quiet mode At clock stop or clock slow down, or the length of the last stop frame of serial interrupt cycle being 2 clock cycles, it will be the quiet mode. In this mode the SERIRQ is driven to "L" in the 1st clock cycle by device and after the receiving of the rest start frame (Note 1) from host, the IRQ1 Frame , IRQ12 Frame or frames selected in each channel will be asserted. Note 1: If the sum of length of "L" that is driven by the device in the 1st clock cycle and by the host in the rest clock cycles is within 4-8 clock cycles, the start frame will be detected. If the sum of length of "L" is less than 4 clock cycles or more than 9 clock cycles, the start frame will not be detected and the next start (the falling edge of SERIRQ) is waited.
Start frame (Note1)
IRQ0 frame
IRQ1 frame
IRQ2 frame
IRQ3 frame
LCLK SERIRQ line System*SERIRQ output Device*SERIRQ output Driver source Device side System side Device side
Note1 . The start frame is set to 4 clock as setting example
Fig.SI-10 Timing diagram of quiet mode
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M16C/6K9 Group
Serial Interrupt Output
(3) Clock restart/ stop inhibition request
_______________
Asserting the CLKRUN signal can request to restart or maintain the clock which stops or slows down or request the host to tend to stop or slow down. Fig.SI-11 shows an example of timing of clock restart request, Fig.SI-12 shows an example of timing of clock stop inhibition request. Clock restart operation Setting the clock restart bit of serial interrupt control register0 to "1" will request the clock restart if the clock has slowed down or stopped at serial interrupt request.
LCLK CLKRUN line System*CLKRUN Device*CLKRUN SERIRQ line System*SERIRQ Device*SERIRQ Restart frame Start frame
f1 Serial interrupt request Internal Interrupt restart request signal
Fig.SI-11 Timing diagram of clock restart request
Clock stop inhibition request Setting the clock stop inhibition bit of serial interrupt control register0 to "1" will request the inhibition of clock stop if the clock tends to stop or slow down during all the period of serial interrupt output.
Clock CLKRUN line System*CLKRUN Device*CLKRUN SERIRQ line Serial interrupt request Inhibition request A cycle of serial interrupt
Internal Interrupt Inhibition request signal
Fig.SI-12 Example of timing of clock stop inhibition request
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M16C/6K9 Group
MULTI-MASTER I2C-BUS Interface
MULTI-MASTER I2C-BUS Interface
The multi-master I2C-BUS interface is a serial communication circuit based on Philips I2C-BUS data transfer format. 3 independent channels, with both arbitration lost detection and a synchronous functions, are built in for the multi-master serial communication. Fig.GC-1 shows a block diagram of the multi-master I2C-BUS interface and Table.GC-1 lists the multi-master I2C-BUS interface functions. The multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register 1, I2C control register 2, the I2C status register, the I2C start/stop condition control register and other control circuits. Note 1: 2 independent channels exist in M306K9F8LRP. Table.GC-1 Multi-master I2C-BUS interface functions Item Function Based on Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode Based on Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1kHz to 400kHz (at VIIC = 4MHz)
Format
Communication mode
SCL clock frequency
*VIIC=I2C system clock
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b7
Interrupt request signal (SCLSDAIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
M16C/6K9 Group
I2C Control register 1
Fig.GC-1 Block diagram of multi-master I2C-BUS interface
I2C address register b0
Interrupt generating circuit Interrupt request signal (I2CIRQ)
Jun 06, 2003
S0D
Address comparator Data control circuit
b7
b0
S3D
ICK1
ICK0 SCLM SDAM
WIT
SIM
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b7
I2C data shift register S0
Interrupt generating circuit
Serial data
(SDA) b7
Noise elimination circuit b0
b0
AL AAS AD0 LRB MST TRX BB PIN
S2D AL
circuit
STSP SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 SEL
MULTI-MASTER I2C-BUS Interface
I C start/stop condition control register Internal data bud
2 I C control register 2
2
S1
I 2 C status register
BB
circuit S4D
TOSEL TOF TOE
2
Serial
Timeout detection circuit
clock (SCL) b7 b0
FAST ACK MODE CCR4 CCR3 CCR2 CCR1 CCR0 BIT
b7
TISS
Noise elimination circuit
ACK
2 S2 I C clock control register
Clock control circuit
I C control register 0 S1D
10BIT SAD
b0
ALS System clock select circuit ICK1,ICK0=1,0 1/2 ICK1,ICK0=0,1 ICK1,ICK0=0,0 ICK1,ICK0=1,1 1/2 1/2 1/2 f1 Bit count ES0 BC2 BC1 BC0
Clock division I2 C system clock (VIIC)
ICCK(External clock)
M16C/6K9 Group
MULTI-MASTER I2C-BUS Interface
I2C Data Shift Register
The I2C data shift register (address 032016, 033016, 031016) is an 8-bit shift register to store receiving data and write transmission data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The timing of storing received data to this register is shown in figure GC-3.The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit : bit 3 of address 032316, 033316, 031316) of the I2C control register 0 is "1". The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 032816, 033816, 031816) are "1", the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the value of ES0 bit.
I C data shift register
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S0i(i=0,1,2)
Address 032016,033016,031016
When reset --
Function Transmission data /receiving data are stored. In the master transmission mode, the start condition/ stop condition are triggered by writing data to the register (refer to the section on the method to generate the start/stop condition). The transmission/receiving are started synchronized with SCL.
RW
Note
Note The write is only enabled when bus interface enable bit (ES0 bit) is "1". Because the register is used both for storing transmission data/receiving data, the transmission data should be written after the receiving data are read out before writing transmission data to this register.
Fig.GC-2 I2C data shift register
SCL SDA
tdfil
Internal SCL Internal SDA
tdfil : Noise elimination circuit delay time
1 to 2 VIIC cycle
tdfil
Shift clock
tdsft
Storing data at shift clock rising edge.
tdsf : Shift clock delay time 1 VIIC cycle
Fig.GC-3 The timing of receiving data stored to I2C data shift register
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MULTI-MASTER I2C-BUS Interface
I2C Address Register
The I2C address register (address 032216, 033216, 031216) consists of a 7-bit slave address and a read/ write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. *Bit 0: Read/write bit (RBW) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first byte address data to be received are compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected. *Bits 1 to 7: Slave address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I C address register
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S0Di(i=0,1,2)
Address 032216,033216,031216
When reset 000000002
Bit Symbol
RBW
Bit name
Read/Write bit
Function
This bit is using for comparing with receiving address data in the 10-bit address mode. (Note) For comparing with received address data
R
W
SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6
Slave address
Note.The RBW bit is cleared to "0" automatically when stop condition is detected
Fig.GC-4 I2C address register
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MULTI-MASTER I2C-BUS Interface
I2C Clock Control Register
The I2C clock control register 0,1 (address 032416, 033416, 031416) is used to set ACK control, SCL mode and SCL frequency. *Bits 0 to 4: SCL frequency control bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table GC-2. *Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0", the standard clock mode is selected. When the bit is set to "1" , the high-speed clock mode is selected. When connecting to the bus with the high-speed mode I2C-BUS standard (maximum 400 kbits/s), set 4 MHz or more to I2C system clock(VIIC). *Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock is generated. When this bit is set to "0", the ACK return mode is selected and SDA goes to "L" at the occurrence of an ACK clock. When the bit is set to "1", the ACK nonreturn mode is selected. The SDA is held in the "H" status at the occurrence of an ACK clock. However, when the slave address agrees with the address data in the reception of address data at ACK BIT = "0", the SDA is automatically made "L" (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made "H" (ACK is not returned). *ACK clock: Clock for acknowledgment *Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which responses to the data transferring. When this bit is set to "0", the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to "1", the ACK clock mode is selected and the master generates an ACK clock at the completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA "H") and receives the ACK bit generated by the data receiving device. Note: Except for ACK bit (ACKBIT), do not write data into the I2C clock control register during transfer. If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred normally.
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MULTI-MASTER I2C-BUS Interface
I C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S2i(i=0,1,2)
Address 032416,033416,031416
When reset 000000002
Bit Symbol
CCR0 CCR1 CCR2 CCR3 CCR4 FAST MODE ACK BIT ACK
Bit name
SCL frequency control bits
Function
Refer to table.GC-2
RW
SCL mode specification bit ACK bit ACK clock bit
0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned 1 : ACK is not returned 0 : No ACK clock 1 : ACK clock
Fig.GC-5 I2C clock register
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MULTI-MASTER I2C-BUS Interface
Table.GC-2 Set values of I2C clock control register and SCL frequency Setting value of CCR4 to CCR0 SCL frequency (at VIIC=4MHz, unit : kHz) (Note1) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 0 0 0 1 1 - (Note2) 333 0 0 1 0 0 - (Note2) 250 0 0 1 0 1 100 400 (Note3) 0 0 1 1 0 83.3 166 500 / CCR value 1000 / CCR value (Note3) (Note3) 1 1 1 0 1 17.2 34.5 1 1 1 1 0 16.6 33.3
Rev.1.00
1
Notes1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at VIIC = 4 MHz). "H" duration of the clock fluctuates from -4 to +2 machine cycles in the standard clock mode, and fluctuates from -2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because "L" duration is extended instead of "H" duration reduction. These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using these setting value, use VIIC = 4 MHz or less. Refer to I2C system clock selection bits (bit 6,7 of I 2C control register 1) on VIIC. 3: The data formula of SCL frequency is described below: VIIC/(8 X CCR value) Standard clock mode VIIC/(4 X CCR value) High-speed clock mode (CCR value 5) VIIC/(2 X CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of VIIC frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
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1
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1
1
16.1
32.3
M16C/6K9 Group
MULTI-MASTER I2C-BUS Interface
I2C Control Register 0
The I2C control register 0 (address 032316, 033316, 031316) of channel 0, 1 controls data communication format. *Bits 0 to 2: Bit counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK bit (bit 7 of address 032416, 033416, 031416)) have been transferred, and BC0 to BC2 are returned to "0002". Also when a START condition is detected, these bits become "0002" and the address data is always transmitted and received in 8 bits. *Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to "0", the interface is disabled and the SDA and the SCL become high-impedance. When the bit is set to "1", the interface is enabled. When ES0 = "0", the following is performed. 1)Set MST = "0", TRX = "0", PIN = "1", BB ="0", AL = "0", AAS = "0", and AD0 = "0", of I 2C status register (Address : 032816, 033816, 031816) 2)Writing data to I2C data shift register (Address : 032016, 033016, 031016) is inhibited. 3)The TOF bit of I2C control register (Address : 032716, 033716, 031716) is cleared to "0" 4)I2C system clock (VIIC) is stopped and the interval counter, flags are initialized. *Bit 4: Data format selection bit (ALS) This bit decides if the recognition of slave address should be processed. When this bit is set to "0", the addressing format is selected, so that address data will be recognized. The transfer will be processed only when a comparison is matched between the salve address and the address data or a general call is received (refer to the item of bit 1 of I2C status register: general call detection flag). When this bit is set to "1", the free data format is selected, so that slave address will not be not recognized. *Bit 5: Addressing format selection bit (DBIT SAD) This bit selects a slave address specification format. When this bit is set to "0", the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 032216, 033216, 031216) are compared with address data. When this bit is set to "1", the 10-bit addressing format is selected, and all the bits of the I2C address register are compared with address data. *Bit 6: I2C-BUS interface reset bit (IHR) The bit is used to reset I2C-BUS interface circuit in the case that the abnormal communication occurs. When the ES0 bit is"1" (I2C-BUS interface is enabled), writing"1" to the IHR bit makes a H/W reset. Flags are processed as follows: 1)Set MST = "0", TRX = "0", PIN = "1", BB ="0", AL = "0", AAS = "0", and AD0 = "0", of I 2 C status register (Address : 032816, 033816, 031816) 2)The TOF bit of I2C control register (Address : 032716, 033716, 031716) is cleared to "0" 3)The interval counter, flags are initialized. After writing"1" to IHR bit, the circuit reset processing will be finished in Max. 2.5 VIIC cycles and IHR bit will be automatically cleared to "0". Fig.GC-6 shows the reset timing. *Bit 7: I2C-BUS interface pin input level selection bit This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. When this bit is set to"1" the P60,P61/P62,P63/P76,P77 will become SMBus input level.
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MULTI-MASTER I2C-BUS Interface
The signal of writing "1" to IHR bit
IHR bit
The reset signal to I2 C-BUS interface circuit
2.5 VIIC cycles
Fig.GC-6 The timing of reset to the I2C-BUS interface circuit
I 2 C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol S1Di(i=0,1,2)
Address 032316,033316,031316
When reset 000000002
Bit Symbol
BC0
Bit name
Bit counter (Number of transmitting/ receiving bits) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 : : : : : : : :
Function
(Note) 8 7 6 5 4 3 2 1
RW
BC1
BC2
ES0
I 2C-BUS interface enable bit
0 : Disable 1 : Enable 0 : Addressing format 1 : Free data format
ALS
Data format selection bit
DBIT SAD
Addressing format selection bit I2 C-BUS interface reset bit
2
0 : 7-bit addressing format 1 : 10-bit addressing format 0 : Release of reset (auto) 1 : Reset 0 : I 2 C-BUS input 1 : SMBUS input
IHR
TISS Note
I C-BUS interface pin input level selection bit
In the following status, the bit counter will be cleared automatically *Start condition/stop condition is detected *Right after the completion of 1 byte data transmission *Right after the completion of 1 byte data receiving
Fig.GC-7 I2C control register
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M16C/6K9 Group
MULTI-MASTER I2C-BUS Interface
I2C Status Register
The I2C status register (address 032816, 033816, 031816) controls the I2C-BUS interface status. The loworder 6 bits are read-only if it is used for status check. The high-order 2 bits can be both read and written. Regarding to the function of writing to the low-order 6 bits, refer to the method of start condition/stop condition generation described later. *Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0". If ACK is not returned, this bit is set to "1". Except in the ACK mode, the last bit value of received data is input. The bit will be "0" by executing a write instruction to the I2C data shift register (address 032016, 033016, 031016). *Bit 1: General call detecting flag (AD0) When the ALS bit is "0", this bit is set to "1" when a general call* whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition, START condition, or ES0 is"0", or reset. *General call: The master transmits the general call address "0016" to all slaves. *Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is "0". 1)In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions: * The address data, which following the start conduction, is same with upper bits data of I 2C address register(Address 032216, 033216, 031216) * A general call is received. 2)In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition: * When the address data is compared with the I2C address register (8 bits consisting of slave address and RBW bit), the first bytes agree. 3)This bit is set to "0" by executing a write instruction to the I2C data shift register (address 032016, 033016, 031016) when ES0 is set to "1". The bit is also set to "0" when ES0 is set to "0" or when reset. *Bit 3: Arbitration lost* detecting flag (AL) In the master transmission mode, when the SDA is made "L" by any other device, arbitration is judged to have been lost, so that this bit is set to "1". At the same time, the TRX bit is set to "0". Immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0". The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to detect the agreement between its own slave address and address data transmitted by another master device. The bit is cleared to "0" if writing to I2C data shift register (address 032016, 033016, 031016) when ES0 is "1". The bit is also cleared to "0" when ES0 is set to "0" or when reset. *Arbitration lost: The status in which communication as a master is disabled.
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M16C/6K9 Group
MULTI-MASTER I2C-BUS Interface
*Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. After each byte data is transmitted, the PIN bit changes from "1" to "0". At the same time, an I2C interrupt request signal occurs to the CPU. The PIN bit is set to "0" synchronized with the falling edge of the last internal transmitting clock (including the ACK clock) and an interrupt request signal occurs synchronized with the falling edge of the PIN bit. When the PIN bit is "0", the SCL is kept in the "0" state and clock generation is disabled. In the ACK clock enable mode, if WIT bit (bit 1 of I2C control register 1) is set to "1", synchronized with the falling edge of last bit clock and ACK clock, PIN bit becomes to "0" and I2C interrupt request is generated (Refer to the description on bit 1 of I2C control register 1: the data reception completion interrupt enable bit). Fig.GC-9 shows the timing of I2C interrupt request generation. The bit is read-only, the value should be "0" in writing. The PIN bit is set to "0" in one of the following condition: *Executing a write instruction to the I2C data shift register (address 032016, 033016, 031016). *Executing a write instruction to the I2C clock control register (Address : 032416, 033416, 031416) (only when WIT is "1" and internal WAIT flag is "1") *When the ES0 bit is "0" *At reset The PIN bit is set to "0" in one of the following condition: *Immediately after the completion of 1-byte data transmission (including arbitration lost is detected) *Immediately after the completion of 1-byte data reception *In the slave reception mode, with ALS = "0" and immediately after the completion of slave address agreement or general call address reception *In the slave reception mode, with ALS = "1" and immediately after the completion of address data reception *Bit 5: Bus busy flag (BB) This bit indicates the in-use status the bus system. When this bit is set to "0", bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to "1" by detecting the start condition, and is set to "0" by detecting the stop condition. The condition of the detecting is set by the start/stop condition setting bits (SSC4-SSC0) of the I2C start/stop condition control register (address 032516, 033516, 031516). When the ES0 bit (bit 3) of the I2C control register (address 032316, 033316, 031316) is "0" or reset, the BB flag is set to "0". For the writing function to the BB flag, refer to the sections "START Condition Generating Method" and "STOP Condition Generating Method" described later. *Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is "0", the reception mode is selected and the data from a transmitting device is received. When the bit is "1", the transmission mode is selected and address data and control data are output onto the SDA synchronized with the clock generated on the SCL. This bit can be set/reset by software or hardware. This bit is set to "1" by hardware in the following condition: In slave mode with ALS = "0", if the AAS flag is set to "1" after the address data reception and the received ___ R/W bit is "1". This bit is set to "0" by hardware in one of the following conditions: *When arbitration lost is detected. *When a STOP condition is detected. *When a start condition is prevented by the start condition duplication preventing function (Note). *When a start condition is detected with MST = "0". *When ACK non-return is detected with MST = "0". *When ES0 = "0". *At reset
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*Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0", the slave is specified, so that a START condition and a STOP condition generated by the master are received. The data communication is performed synchronized with the clock generated by the master. When this bit is "1", the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to "0" by hardware in one of the following conditions. *Immediately after the completion of 1-byte data transfer when arbitration lost is detected. *When a STOP condition is detected. *Writing a start condition is prevented by the start condition duplication preventing function (Note). *At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to "1" at the same time after confirming that the BB flag is "0" in the procedure of a START condition occurrence. However, when a START condition by an other master device occurs and the BB flag is set to "1" immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. Refer to the method on the start condition generation in detail.
I C status register
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S1i(i=0,1,2)
Address 032816,033816,031816
When reset 0001000X2
Bit symbol
LRB AD0 AAS AL PIN BB TRX
Bit name
Last receive bit General call detecting flag Slave address comparison flag Arbitration lost detection flag I 2 C-BUS interface interrupt request bit Bus busy flag Communication mode specification bits
Function
0 : Last bit = "0" 1 : Last bit = "1" 0 : No general call detected 1 : General call detected 0 : Address disagreement 1 : Address agreement 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave receive mode 1 : Slave transmit mode 0 : Master receive mode 1 : Master transmit mode
RW
(Note1)
(Note1)
(Note1)
(Note1)
(Note2)
(Note1)
(Note3)
MST
(Note3)
Note1.This bit is read only if it is used for the status check. How to write this bit, please refer to start condition/stop condition generating method. Note2.The bit can be read and only can be written with "0" by software. Note3.Refer to the method of start condition generation on how to write these bits. How to write this bit, please refer to start condition/stop condition generating method.
Fig.GC-8 I2C status register
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SCL
PIN flag
I2CIRQ
Fig.GC-9 Interrupt request signal generating timing
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I2C0, I2C1 control register 1
I2C control register 10, 11, 12 (address 032616, 033616, 031616) controls I2C-BUS interface circuit. *Bit 0 : Interrupt enable bit by STOP condition (SIM ) It is possible for I2C-BUS interface to request an interrupt by detecting a STOP condition. If the bit set to "1", an interrupt from I2C-BUS interface occurs by detecting a STOP condition ( There is no change for PIN flag) *Bit 1: Interrupt enable bit at the completion of data receiving (WIT) When with-ACK mode (ACK bit = "1") is specified, by enabling the interrupt at the completion of data receiving (WIT bit = "1"), the I2C interrupt request occurs and PIN bit becomes "0" synchronized with the falling edge of last data bit clock. SCL is fixed "L" and the generation of ACK clock is suppressed. Table GC-3 and Fig.GC-10 show the I2C interrupt request timing and the method of communication restart. After the communication restart, synchronized with the falling edge of ACK clock, PIN bit becomes to "0" and I2C interrupt request occurs. Table.GC-3 Timing of interrupt generation in data receiving The timing of I2C interrupt generation The method of communication restart 1)Synchronized with the falling edge of the The execution of writing to ACKBIT of I2C clock control last data bit clock register. (Do not write to I2C data shift register. The processing of ACK clock would be incorrect.) 2)Synchronized with the falling edge of the The execution of writing to I2C data shift register ACK clock The state of internal WAIT flag can be read out by reading the WIT bit. The internal WAIT flag is set after writing to I2C data shift register, and it is reset after writing to I2C clock control register. Consequently, which of the timing 1) and 2) of interrupt request occurring can be understood. (See Fig.GC-10)In the cases of transmission and address data reception immediately after the START condition, the interrupt request only occurs at the falling edge of ACK clock regardless of the value of WIT bit and the WAIT flag remains the reset state. Write "0" to WIT bit when in NACK is specified. (ACK bit = "0")
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*Bits 2,3 : Port function selection bits PED, PEC When ES0 bit of I2C control register 0 is set to "1", P61/P63 and P60/P62 function as SCL and SDA respectively. However, if PED is set to "1", SDA functions as output port so as to SCL if PEC is set to "1". In this case, if "0" or "1" is written to the port register, the data can be output on to the I2C-BUS regardless of the internal SCL/SDA output signals. The functions of SCL/SDA are returned back by setting PED/PEC to "1" again. If the ports are set in input mode, the values on the I2C-BUS can be known by reading the port register regardless of the values of PED and PEC.Table GC-4 shows the port specification. Table.GC-4 Ports specifications Pin name P60/P62 ES0 bit 0 1 1 P61/P63 ES0 bit 0 1 1 PED bit 0 1 PEC bit 0 1
P6 port direction register
Function Port I/O function SDA I/O function SDA input function, port output function Function Port I/O function SCL I/O function SCL input function, port output function
0/1 P6 port direction register
0/1 -
*Bits 4,5 : SDA/SCL logic output value monitor bits SDAM /SCLM It is possible to monitor the logic value of the SDA and SCL output signals from I2C-BUS interface circuit. SDAM can monitor the output logic value of SDA. SCLM can monitor the output logic value of SCL. The bits are read-only. Write "0" if in writing (Writing "1" is reserved) *Bits 6,7 : I2C system clock selection bits ICK0, ICK1 These bits select the basic operation clock of I2C-BUS interface circuit. It is possible to select I2C system clock VIIC among 1/2,1/4 and 1/8 of main clock f(XIN) and 1/2 of external I2C clock (ICCK)
Table.GC-5 I2C system clock selecting bits ICK1 ICK0 I2C system clock 0 0 VIIC = 1 / 2f1 0 1 VIIC = 1 / 4f1 1 0 VIIC = 1 / 8f1 1 1 VIIC = 1 / 2ICCK Note: f1 = f(XIN) ICCK = External I2C clock
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*The address reception in STOP mode /WAIT mode It is possible for I2C-BUS interface to receive address data even in STOP mode or in WAIT mode. However the I2C system clock VIIC should be supplied. Table.GC-6 shows the setting list. Table.GC-6 Clock setting to the I2C system in different operation mode. Mode STOP mode WAIT mode The setting content The external clock is selected as the I2C system clock ( ICK1 = 1, ICK0 = 1) and the external I2C clock is supplied by ICCK. The external clock is selected as the I2C system clock ( ICK1 = 1, ICK0 = 1) and the external I2C clock is supplied by ICCK. Select the peripheral function clock stop bit CMO2 (bit 2 of the system clock control register 0, address : 000616) to the state of not stopping f1,f8,f32 (CMO2 = 0) when in WAIT mode, and then execute the WAIT command. The external clock is selected as the I2C system clock ( ICK1 = 1, ICK0 = 1) and the external I2C clock is supplied by ICCK.
Low power consumption mode
When in reception mode, ACK bit = "1" WIT bit = "0"
SCL SDA ACKBIT PIN flag Internal WAIT flag I2C interrupt request signal The writing signal of I2C data shift register 7 clock 7 bit 8 bit 8 clock ACK clock ACK bit 1 clock 1 bit
When in reception mode, ACK bit = "1" WIT bit = "1"
SCL SDA ACKBIT PIN flag Internal WAIT flag I2C interrupt request signal The writing signal of I2C data shift register The writing signal of I2C clock control register 7 clock 7 bit 8 bit 8 clock ACK clock 1 bit
Note. Do not write to I2C clock control register except bit ACKBIT.
Fig.GC-10 The timing of the interrupt generation at the completion of data reception
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I C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S3Di(i=0,1,2)
Address 032616,033616,031616
When reset 001100002
Bit Symbol
SIM
Bit name
The interrupt enable bit of STOP condition detection
Function
0 : Disable the interrupt of STOP condition detection 1 : Enable the interrupt of STOP condition detection 0 : Disable 1 : Enable When in NACK setting (ACK bit = "0") please write "0"
RW
WIT
The interrupt enable bit of at the completion of data reception
PED
SDAi/Port function switching bit
0 : SDA I/O pin(enable ES0 = 1) 1 : GPIO(enable ES0 = 1)
PEC
SCLi/Port function switching bit The logic value monitor bit of SDA output The logic value monitor bit of SCL output I 2 C system clock selection bits
0 : SCL I/O pin(enable ES0 = 1) 1 : GPIO(enable ES0 = 1) 0 : SDA output logic value = "0" 1 : SDA output logic value = "1" 0 : SCL output logic value = "0" 1 : SCL output logic value = "1" b7 b6 0 0 : VIIC=1/2f1 0 1 : VIIC=1/4f1 f1=f(XIN) 1 0 : VIIC=1/8f1 1 1 : VIIC=1/2ICCK ICCK=External I2C clock
SDAM
SCLM ICK0
ICK1
Fig.GC-11 I2C control register 1
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MULTI-MASTER I2C-BUS Interface
I2C control register 2
I2C0, 1 control register 2 (address: 032716, 033716, 031716) control the detection of communication abnormality. In I2C-BUS communication, the data transfer is controlled by the SCL clock signal. The devices will stop in the communication state if SCL stops during transfer. So if the SCL clock stops in "H" state for a period of time, the I2C-BUS interface circuit can detect the time out and request an I2C interrupt. Please see Fig.GC-12.
SCL clock stop ("H") SCL SDA BB flag Internal counter start signal Internal counter stop, reset signal The time of timeout detection Internal counter overflow signal I2C interrupt request signal 1 bit 1 clock 2 bit 2 clock 3 bit 3 clock
Fig.GC-12 The timing of timeout detection *Bit0: Time out detection function enable bit (TOE) The bit enables timeout detection function. By setting this bit to "1", the I2C interrupt request signal will be generated if the SCL clock stops in "H" state for a period of time during bus busy (BB flag ="1"). The time of time out detection which is selected by timeout detection time selection bit (TOSEL) with long time mode or short time mode will be calculated by internal counter. When time out is detected, please set "0" to I2C-BUS interface enable bit (ES0) and then process initialization. *Bit1: Time out detection flag (TOF ) The bit is the flag showing timeout detection status. If the time which is calculated by the internal counter overflows, the time out detection flag (TOF) becomes to "1", and at the same time the I2C interrupt request signal is generated. *Bit2: timeout detection time selection bit (TOSEL) The bit selects timeout detection time from long time and short time mode. If TOSEL = "0", the long time mode; TOSEL = "1", the short mode is selected respectively. The long time is up counted by 16 bits counter and the short time is up counted by 14 bits counter based on I2C system clock (VIIC). Table GC-7 shows examples of the timeout detection time.
Table.GC-7 Examples of timeout detection time VIIC(MHz) 4 2 1 Long time mode 16.4 32.8 65.6
(Unit: ms) Short time mode 4.1 8.2 16.4
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I Control register 2
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S4Di(i=0,1,2)
Address 032716,033716,031716
When reset 000000002
Bit symbol
TOE TOF TOSEL
Bit name
Timeout detection function enable bit Timeout detection flag Timeout detection time selection bit
Function
0 : Disable 1 : Enable 0 : Not detected 1 : Detected 0 : Long time 1 : Short time
R
W
Nothing is assigned. Can not be written in the value is "0" SCPIN STOP condition detection interrupt request bit 0 : No interrupt request 1 : Interrupt request
Fig.GC-13 I2C control register 2 *Bit7: STOP condition detection interrupt request bit (SCPIN) The bit monitors the stop condition detection interrupt. The bit becomes to "1" when I2C-BUS interface interrupt is generated by the detecting of STOP condition. Writing "0" clears the bit and "1" can not be written.
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MULTI-MASTER I2C-BUS Interface
I2C START/STOP condition control register
I2C START/STOP condition register(address 032516, 033516, 031516) controls the detection of START/STOP condition. *Bit0-Bit4: START/STOP condition setting bits (SSC4-SSC0) Because the release time, set up time and hold time of SCL is calculated on the base of I2C system clock(VIIC). The detecting condition changes depending on the oscillation frequency and I2C system clock selecting bits. It is necessary to set the suitable value of START/STOP condition setting bits (SSC4-SSC0) so that obtain the release time, set up time and hold time corresponding to the system clock frequency. Refer to Table GC-11. Do not set odd number or "000002" to START/STOP condition setting bits. The recommended setting value to START/STOP condition setting bits (SSC4-SSC0) at each oscillation frequency under standard clock mode is shown in Table. GC-8. The detection of START/STOP condition starts immediately after the setting of ES0=1. *Bit5: SCL/SDA interrupt pin polarity selection bit (SIP) The interrupt can be generated by detecting the rising edge or the falling edge of SCL pin or SDA pin. SCL/SDA interrupt pin polarity selection bit selects the polarity of SCL pin or SDA pin for interrupt. *Bit6 : SCL/SDA interrupt pin selection bit (SIS) SCL/SDA interrupt pin selection bit selects either SCL pin or SDA pin as SCL/SDA interrupt enable pin. Note: The SCL/SDA interrupt request may be set when the setting of I2C-BUS interface enable bit ES0 changes. Thus set the interrupt disable before the setting of SCL/SDA interrupt pin polarity selection bit (SIP) and SCL/SDA interrupt selection bit(SIS). After that reset "0" to the interrupt request bit before enabling the interrupt. *Bit7: START/STOP condition generation selecting bit (STSPSEL) The bit selects the length of set up/hold time when START/STOP condition occurs. The length of set up/hold time is based on the I2C system clock cycles. Refer to Table GC-9. Set the bit to "1" if I2C system clock frequency is over 4MHz.
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I C start/stop condition control register
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol S2Di(i=0,1,2)
Address 032516,033516,031516
When reset 000110102
Bit Symbol
SSC0 SSC1 SSC2 SSC3 SSC4
Bit name
START/STOP condition setting bits
Function
The setting of the detecting condition of START/STOP condition.Refer to Table GC-8. Note: Prohibit the setting of "000002" and odd value
RW
SIP
SCL/SDA interrupt pin polarity selection bit SCL/SDA interrupt pin selection bit START/STOP condition generation selection bit
0 : Active in falling edge 1 : Active in rising edge 0 : SDA enable 1 : SCL enable 0 : Setup/hold time short mode 1 : Setup/hold time long mode
SIS
STSP SEL
Fig.GC-14 I2C start/stop condition control register
Table.GC-8 Recommended setting value (SSC4 - SSC0) start/stop condition at each oscillation frequency Oscillation I2C system I2C system SSC4-SSC0 SCL release Setup time Hold time f(XIN) (MHz) clock selection clock(MHz) time(cycle) (cycle) (cycle) 10 1 / 2f1 5 XXX11110 6.2s (31) 3.2s (16) 3.0s (15) 8 1 / 2f1 4 XXX11010 6.75s(27) 3.5s (14) 3.25s(13) XXX11000 6.25s(25) 3.25s(13) 3.0s (12) 8 1 / 8f1 1 XXX00100 5.0s (5) 3.0s (3) 2.0s (2) 4 1 / 2f1 2 XXX01100 6.5s (13) 3.5s (7) 3.0s (6) XXX01010 5.5s (11) 3.0s (6) 2.5s (5) 2 1 / 2f1 1 XXX00100 5.0s (5) 3.0s (3) 2.0s (2) Note: Do not set odd value or "000002" to START/STOP condition setting bits.
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START Condition Generation Method
When ES0 bit of the I2C control register is "1" and the BB flag of I2C status register is "0", writing "1" to the MST, TRX, and BB bits and "0" to the PIN and low-order 4 bits of the I2C status register (address 032816, 033816, 031816) simultaneously enters the standby status to generate the start condition. The start condition is generated after writing slave address data to the I2C data shift register. After that, the bit counter becomes "0002" and 1 byte SCL are output. The START condition generation timing is different in the standard clock mode and the high-speed clock mode. Refer to Fig.GC-17 the START condition generation timing diagram, and Table GC-9 the START condition generation timing table.
Interrupt disable
No BB=0?
Yes S1i=E016 Start condition standby status setting
S0i=Data
Start condition trigger occur. Data=Slave address data
Interrupt enable
Fig.GC-15 Start condition generation flow chart
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Function of protection of duplicate START condition
It is necessary to verify that the bus is not in use via BB flag before setting up a START condition. However, there is a possibility that right after the verification of BB flag, the BB flag becomes to "1" because a START condition is generated by another master device .In this case, the function to interrupt the start condition is built in. When the function starts, it works as follows: *The prohibition of setting up START condition standby If the START condition standby has been set up, releases it and resets the bits of MST and TRX. *The prohibition of writing to the I2C data shift register (The prohibition of generating a START condition trigger) *If the generation of start condition is interrupted, sets the AL flag. The function of protection of duplicate START condition is valid from the falling edge of SDA of START condition to the completion of slave reception. Fig.GC-16 shows the valid period of the function of protection of duplicate START condition.
SCL SDA BB flag 1 bit
1 clock
2 clock 2 bit
3 clock 3 bit
8 clock 8 bit
ACK clock
ACK bit
The valid period of protection of duplicate START condition
Fig.GC-16 The valid period of the function of protection of duplicate START condition
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STOP Condition Generation Method
When the ES0 bit of the I2C control register is "1", writing "1" to the MST and TRX bits, and "0" to the BB, PIN and low-order bits of the I2C status register simultaneously enters the standby status to generate the stop condition. The stop condition is generated after writing dummy data to the I2C data shift register. The STOP condition generation timing is different in the standard clock mode and the high-speed clock mode. Refer to Fig.GC-18, the STOP condition generation timing diagram, and Table GC-9, the STOP condition generation timing table. Do not write data to I2C status register and I2C data shift register, before BB flag becomes to "0" after the instruction to generate the stop condition to avoid the influence on generating STOP condition waveform.
I2C data shift register write signal
SCL SDA
Setup time
Hold time
Fig.GC-17 Start condition generation timing diagram
I2C data shift register write signal
SCL SDA
Setup time
Hold time
Fig.GC-18 Stop condition generation timing diagram Table.GC-9 Start/Stop generation timing table Start/Stop condition generation selection bit Setup "0" time "1" hold "0" time "1" Note: VIIC = 4MHz Item Standard clock mode 5.0s (20 cycle) 13.0s (52 cycle) 5.0s (20 cycle) 13.0s (52 cycle) High-speed clock mode 2.5s (10 cycle) 6.5s (26 cycle) 2.5s (10 cycle) 6.5s (26 cycle)
As mentioned above, Writing "1" to MST and TRX bits. Writing "1" or "0" to BB bit, writing "0" to PIN and low-order 4 bits, simultaneously sets up the START or STOP condition standby. It releases SDA in START condition standby, makes SDA to "L" in STOP condition standby. The signal of writing to data shift register triggers the generation of START/STOP condition. In the case of setting MST, and TRX to "1" but do not want to generate a START/STOP condition. Write "1" to the low-order 4 bits simultaneously. Fig.GC-10 illustrates the function of writing to status register. Table.GC-10 The function of writing to status register The value of the data writing to status register MST TRX BB PIN AL AAS AS0 LRB 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0/1 0/1 0 1 1 1 1 Function
Setting up the START condition stand by in master transmission mode Setting up the STOP condition stand by in master transmission mode Setting up the communication mode (refer to the description on I2C status register)
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START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in Fig.GC-19, GC-20 and Table.GC-11 The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy with three conditions: SCL release time, setup time, and hold time (see Table.GC-11). The BB flag is set to "1" by detecting the START condition and is reset to "0" by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table GC-11, the BB flag set/reset time.
SCL release time
SCL SDA
Setup time
Hold time
BB flag set time
BB flag
Fig.GC-19 Start condition detection timing diagram
SCL release time
SCL SDA
Setup time
Hold time
BB flag reset time
BB flag
Fig.GC-20 Stop condition detection timing diagram
Table.GC-11 Start/Stop generation timing table SCL release time Setup time Hold time BB flag set/reset time Standard clock mode SSC value + 1 cycle (6.25s) SSC value + 1 cycle < 4.0s (3.25s) 2 SSC value cycle < 4.0s (3.0s) 2 SSC value - 1 +2 cycle (3.375s) 2 High-speed clock mode 4 cycle (1.0s) 2 cycle (0.5s) 2 cycle (0.5s) 3.5 cycle (0.875s)
Note: Unit : Cycle number of system clock VIIC SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set "0" or an odd number to SSC value. The value in parentheses is an example when the I2C START/STOP condition control register is set to "1816" at VIIC = 4 MHz.
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MULTI-MASTER I2C-BUS Interface
Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. (1) 7-bit addressing format To adapt the 7-bit addressing format, set the DBIT SAD bit of the I2C control register 0 (address 032316, 033316, 031316) to "0". The first 7-bit address data transmitted from the master is compared with the highorder 7-bit slave address stored in the I2C address register (address 032216, 033216, 031216). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 032216, 033216, 031216) is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Fig.GC-21 (1) and (2). (2) 10-bit addressing format To adapt the 10-bit addressing format, set the DBIT SAD bit of the I2C control register 0 (address 032316, 033316, 031316) to "1". Also set the WIT bit of I2C control register 1 to "1". An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C address register (address 032216, 033216, 031216). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 032016, 033016, 031016) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RBW bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (address 032816, 033816, 031816) is set to "1". After the second-byte address data is stored into the I2C data shift register (address 32016, 33016, 031016), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, write "0" to the ACKBIT to I2C clock control register, to return an ACK. When the address data of the 2 bytes do not agree with the slave address, it does not return an ACK so that makes the finish of the communication by writing "1" to the ACKBIT. If the address data agree with each other, set the RBW bit of the I2C address register (address 032216, 033216, 031216) to "1" by software. This processing can make the 7-bit slave ___ address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2C address register (address 032216, 033216, 031216). For the data transmission format when the 10-bit addressing format is selected, refer to Fig.GC-21(3) and (4).
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MULTI-MASTER I2C-BUS Interface
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address 7 bits
R/W "0"
A
Data
1 - 8 bits
A
Data
1 - 8 bits
A/A
P
(2) A master-receiver receives data from slave-transmitter
S
Slave address 7 bits
R/W "1"
A
Data
1 - 8 bits
A
Data
1 - 8 bits
A
P
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address 1 st 7 bits 7 bits
R/W "0"
A
Slave address 2nd byte 8 bits
A
Data
1 - 8 bits
A
Data
1 - 8 bits
A/A
P
(4) A master-receiver receives data from slave-transmitter with a 10-bit address
S
Slave address 1 st 7 bits 7 bits
R/W "0"
A
Slave address 2nd byte 8 bits
A
Sr
Slave address 1 st 7 bits 7 bits
R/W "1"
A
Data
1 - 8 bits
A
Data
1 - 8 bits
A
P
S : START condition A : ACK bit Sr : Restart condition
P : STOP condition R/W : Read/Write bit
Fig.GC-21 Address data communication format
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MULTI-MASTER I2C-BUS Interface
Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. 1)Set a slave address in the high-order 7 bits of the I2C address register and "0" into the RBW bit. 2)Set the ACK return mode and SCL = 100 kHz by setting "0016" in the I2C control register 1 and "8516" in the I2C clock control register respectively. (f(XIN)=8MHz) 3)Set "0016" in the I2C status register so that transmission/reception mode is initialized. 4)Set a communication enable status by setting "0816" in the I2C control register 0. 5)Confirm the bus free condition by the BB flag of the I2C status register. 6)Set "E016" in the I2C status register to setup a standby of START condition. 7)Set the destination address data for transmission in high-order 7 bit of I2C data shift register and set "0" in the least significant bit. And then a START condition occurs. At this time, SCL for 1 byte and an ACK clock automatically generate. 8)Set transmission data in the I2C data shift register. At this time, an SCL and an ACK clock automatically generate. 9)When transmitting control data of more than 1 byte, repeat step 8). 10)Set "C016" in the I2C status register to setup a STOP condition if ACK is not returned from slave reception side or transmission ends. 11)A STOP condition occurs when writing dummy data to I2C data shift register.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK return mode and using the addressing format is shown below. 1)Set a slave address in the high-order 7 bits of the I2C address register and "0" in the RBW bit. 2)Set the ACK clock mode and SCL = 400 kHz by setting "0016" in the I2C control register 1 and "A516" in the I2C clock control register respectively. (f(XIN)=8MHz) 3)Set "0016" in the I2C status register so that transmission/reception mode is initialized. 4)Set a communication enable status by setting "0816" in the I2C control register 0. 5)When a START condition is received, an address comparison is performed. 6)*When all transmitted addresses are "0" (general call): AD0 of the I2C status register is set to "1" and an interrupt request signal occurs. *When the transmitted addresses agree with the address set in1): ASS of the I2C status register is set to "1" and an interrupt request signal occurs. *In the cases other than the above AD0 and AAS of the I2C status register are set to "0" and no interrupt request signal occurs. 7)Set dummy data in the I2C data shift register. 8)After receiving 1 byte data, it returns an ACK automatically and an interrupt request signal occurs. 9)In the case of whether returning an ACK or not by the content of the received control data, set the WIT bit of I2C control register 1 to "1", and after writing dummy data to I2C data shift register, receives the control data. 10)After receiving 1 byte data, an interrupt request signal occurs, set the ACKBIT to "1" or "0" by reading the content of the data shift register, and then returns or does not return an ACK. 11)When receiving control data of more than 1 byte, repeat step 7) 8) or 7) 10). 12)When a STOP condition is detected, the communication ends.
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Usage precautions
(1) Access to the registers of I2C-BUS interface circuit The precaution of read/write to the control registers of I2C-BUS circuit is as follows. *I2C data shift register (S0i : 032016, 033016, 031016) Do not write the register during transfer. The transfer bit counter will be reset and makes data communication incorrect. *I2C address register (S0Di : address 032216, 033216, 031216) After the detection of a STOP condition, RBW is reset by H/W. Do not read/write the register at the time, because data may become undetermined. Fig.GC-22 shows the RBW bit H/W reset timing. 2C control register 0 (S1Di : address 032316, 033316, 031316). *I After the detection of a START condition or the completion of 1 byte transfer, bit counter (bits BC0 - BC2) is reset by H/W. Do not read/write the register at the time, because data may become undetermined. Fig.GC-23, GC-24 show the bit counter H/W reset timing. 2C clock control register (S2i : address 032416, 033416, 031416) *I Do not write to this register except ACKBIT during transfer. The I2C clock generator will be reset and *I2C makes transfer incorrect. control register 1 (S3Di : address 032616, 033616, 031616) Write I2C system clock selection bits when I2C-BUS interface enable bit (ES0)is in disable state. By reading the data reception completion interrupt enable bit (WIT), the internal WAIT flag will be read. Thus, do not use bit manipulation (read-modify-write instruction) to access the register. 2C status register (S1i : address 032816, 033816, 031816) *I Do not use bit manipulation (read-modify-write instruction) to access the register because all bits of this register are changed by H/W. Do not read/write during the timing when communication mode setting bits MST and TRX are changed by H/W. Data may become undetermined. Fig.GC-22, GC-23, and GC-24 show the change timing of MST and TRX bits by H/W.
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SCL SDA BB flag Bit reset signal Related bits RBW MST TRX 1.5VIIC cycle
Fig.GC-22 The timing of bit reset (The detection of STOP condition)
SCL SDA BB flag Bit reset signal Related bits BC0 - BC2 TRX(slave mode)
Fig.GC-23 The timing of bit reset (The detection of START condition)
SCL PIN bit Bit reset signal Bit set signal
2VIIC cycle The bits referring to set 1VIIC cycle TRX(ALS="0" meanwhile the slave reception R/W bit = "1" The bits referring to reset BC0 - BC2 MST(When in arbitration lost) TRX(When in NACK reception in slave transmission mode)
Fig.GC-24 Bit set/reset timing ( at the completion of data transfer)
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(2) Generation of RESTART condition After 1 byte data transfer, a RESTART condition standby can be set up by writing "E016" to I2C status register and the SDA pin will be released. Wait in software until SDA become "H" stable and then owing to writing to I2C data shift register a START condition trigger will be generated. Fig.GC-25 shows the restart condition generation timing. (3) Limitation of internal clock 0 The registers of I2C-BUS interface circuit can not be read from or written to if the internal clock up selected to sub clock (XCIN, XCOUT) by system clock selection bit (system clock control register 0, address 000616, CMO7 bit). Please select main clock (XIN, XOUT) in read/write.
SCL SDA
8 clock
ACK clock
S1i writing signal ( Set the standby of start condition) S0i writing signal (START condition trigger generation)
Insert software wait
Fig.GC-25 The time of generation of RESTART condition
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PS2 Interface
PS2 Interface
PS2 interface is supported by 3 channels of serial transmission/reception circuit which is based on PS2 standard specifications. There are two signal lines, used by PS2 interface : PS2 data(DAT) and PS2 clock(CLK). The DAT and CLK signal lines are bidirection and should be connected to positive power supply via external pull-up resistors. These two pins are N-channel open drain output. While bus is released, the states of DAT and CLK is "High". Fig.GK-1 shows the system configuration.
Output
Output
DAT Input Input
DAT
Output
Output
CLK Input Input
CLK
Control side
Device side
Fig.GK-1 System configuration
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PS2 Interface
The PS2 interface performs 1 byte data transfer with the format shown in Fig.GK-2. Table GK-1 shows the communication specification.
Table GK-1 Communication specification Item Data transfer format *Start bit *Data bit *Parity bit *Stop bit Transfer clock Reception start condition
Specification : 1 bit : 8 bits (LSB first) : 1 bit (Odd) : 1 bit
Transmission start condition
Transfer abort
Interrupt request generation timing Error detection
Selection function
*Acknowledge : 1 bit (Transmission only) *Using the clock, which is synchronized with the sampling clock of PS2 clock (CLK) *The following conditions should be met for reception start 1) Setting reception enable bit to "1" 2) The detection of "L" on both PS2 clock (CLK) and PS2 data (DAT) lines *The following conditions should be met for transmission start 1) Setting transmission data to PS2i shift register 2) Setting transmission enable bit to "1" *The following conditions should be met for transfer abort 1) Setting transfer interruption bit to "1" 2) The transfer completion flag becomes "1" *In reception: At the completion of stop bit reception *In transmission: At the completion of ACK bit reception. *In transfer interruption: At the completion of transfer interruption *Parity error (In reception) It occurs when there is a parity error in data reception *Framing error (In reception) It occurs when the detection of stop bit of reception data fails. *Abnormal acknowledge reception (In transmission) It occurs when NAK is received from a device side after the data transmission *Sampling clock selection Selecting the clock which samples the PS2 clock (CLK) and PS2 data (DAT)
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In reception Data :8-bit Parity :Odd Stop :1 bit
START D0 D1
10-bit
D2
D3
D4
D5
D6
D7
PARITY
STOP
1 byte data format
In Transmission Data Parity Stop Acknowledge
START
:8-bit :Odd :1 bit :1 bit
D1
11-bit
D0
D2
D3
D4
D5
D6
D7
PARITY
STOP ACK/NAK
1 byte data format
Fig.GK-2 1 byte data format
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PS2 Interface
Fig.GK-3 shows the PS2 interface overall block diagram. Fig.GK-4 shows the transmission/reception block diagram.
Internal data bus
PS2 mode register (02AC16)
Pin selection Control stop
PS2Bi(i=0-2) CLK output DAT output "1" "1"
Ch0
Transmission/ reception section
Interrupt request 0
PS2Ai(i=0-2)
CLK input DAT input
Ch1 "1" "1" Port control section
Transmission/ reception section
Interrupt request 1
f1 Divider
1/4 1/8 1/16 1/32
Sampling clock selection Sampling clock
Ch2
Transmission/ reception section
Interrupt request 2
Fig.GK-3 PS2 interface block diagram
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PS2 Interface
Internal data bus PS2i shift register (02A016,02A416,02A816) DAT output Sampling clock CLK output CLK input
Synchronization Reception start detection circuit Transmission/reception control circuit
Reception process section * Completion detection * Parity generation
DAT input
Reception completion PE & FE Transfer completion process circuit
Shift enable
Reception enable
Transfer abort Transmission enable
Transmission process section Completion detection * Parity generation * Acknowledge reception
Transmission completion Acknowledge result
Communication status flags Error flag refresh
Transfer completion flag refresh
All bits clear Interrupt request PS2i control register (02A216,02A616,02AA16) Internal data bus PS2i status register (02A116,02A516,02A916)
Fig.GK-4 Transmission/reception section block diagram (One channel)
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(1) Register description
q PS2i shift register * Transmission/reception data (1) Data reception The reception data are stored. (2) Data transmission By writing the transmitted data to the register, data transmission is ready to start. PS2 data (DAT) will become "L" automatically (transmission start).
PS2i Shift register
b7 b6 b5 b4 b3 b2 b1 b0
symbol PS20SR PS21SR PS22SR
Address 02A016 02A416 02A816
Reset value 0016 0016 0016
Bit symbol
Bit name
Function Transmission/reception data
RW
Fig.GK-5 PS2i shift register
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q PS2i Control register * Reception enable bit (REN) The data reception is allowed when this bit is set to "1". The PS2 clock (CLK) will become to "H" (reception enable status) automatically. This bit will be cleared to "0" automatically after the completion of data reception and PS2 clock (CLK) will become "L" (reception disable status) . If this bit is needed wants to be cleared after setting it to "1" but before the transfer completion flag is set, set reception enable bit = "0", transfer abort request bit = "0" and proccess the transfer abort simultaneously. * Transmission enable bit (TEN) After writing transmission data to the PS2i shift register, setting the bit to "1" makes data transmission enabled and PS2 clock (CLK) will become "H" automatically (transmission enable status). This bit will be cleared to "0" automatically after the completion of data transmission and PS2 clock (CLK) will become "L" (transmission disable status). If this bit is needed to be cleared after setting it to "1" but before the transfer completion flag is set, set reception enable bit = "0", transfer abort request bit = "0" and proccess the transfer abort simultaneously. * Transfer abort request bit (RSTOP) This bit is used to abort the data transfer procession. At the completion of transfer abort procession, the transfer completion flag and transfer abort flag of PS2i status register are set to "1", the bit is cleared to "0" automatically and PS2 clock (CLK) will become "L" ( reception disable status). After "L" is output to the PS2 clock (CLK), do not execute the following transmission/reception before the device recognizes the transfer abort request.
PS2i control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS20CON PS21CON PS22CON
Address 02A216 02A616 02AA16
Reset Value 0016 0016 0016
Bit Symbol
REN TEN RSTOP
Bit name
Reception enable bit Transmission enable bit Transfer abort request bit
Function
0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : No transfer abort 1 : Transfer abort
RW
Nothing is assigned. Meaningless in writing, "0" in reading.
Fig.GK-6 PS2i control register
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PS2 Interface
qPS2i status register * Transfer completion flag (TI) The flag is set to "1" at the completion of transmission/reception and the completion of transfer abort. The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from "0" to "1". * Receiving flag (RF) The flag is set to "1" during the data reception. The flag is cleared automatically after the data reception or after the transfer abort. * Reception abort incognizable flag (CD) The flag is set in the case that device side can not recognize the abort even if the reception abort is requested. (The flag is set in the period between the completion of data bit 6 reception and the completion of stop bit reception.) The flag is cleared automatically after the completion of data reception or after the completion of transfer abort. Note that during the period when the flag is set, the device side can not recognize the reception abort request even if the tranfer abort is executed. Thus the data that the transfer abort is requested will not be resent from device side. * Transfer status flag (TS) The flag is set to "1" at the completion of data reception. The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from "0" to "1". * Parity error flag (PE) This bit is set to "1" when parity error occurs in received data. The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from "0" to "1". * Framing error / NACK reception flag (FE) At the completion of reception: The flag is set when the detection of stop bit of reception data fails. At the completion of transmission: The flag is set when NAK is received from the device side. The flag is cleared at read out from PS2i shift register, the reception enable bit or the transmission bit is changed from "0" to "1". * Transfer abort completion flag (CC) This bit is set to "1" when transfer abort procession is completed. The flag is cleared at read out from PS2i shift register, or when the reception enable bit or the transmission bit is changed from "0" to "1".
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PS2i status register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS20STS PS21STS PS22STS
Address 02A116 02A516 02A916
Reset Value 0016 0016 0016
Bit Symbol
TI
Bit name
Transfer completion flag
Function
0 : Waiting for transfer, During transfer 1 : Communication complete 0 : Waiting for reception, Reception complete 1 : During receiving
RW
RF
Receiving flag
CD TS PE FE CC
Reception abort incognizable flag Transfer status flag Parity error flag Framing error / NACK reception flag Transfer abort completion flag
0 : Recognizable 1 : Incognizable 0 : Transmission operation 1 : Reception operation 0 : No error 1 : Error 0 : No error 1 : Error 0 : Not abort 1 : Abort
Nothing is assigned. Meaningless in writing, "0" in reading.
Fig.GK-7 PS2i status register
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PS2 Interface
q PS2 mode register * Sampling clock selection bits (SCK0,1) These two bits select clock frequency for sampling PS2 clock (CLK) and PS2 data (DAT). The relation between main clock (XIN) and sampling cycle is shown in table below.
XIN 8MHz 5MHz
Setting value
1/4 0.5 0.8
1/8 1.0 1.6
1/16 2.0 3.2
1/32 4.0 6.4
Sampling clock , which samples each line periodically, is used for avoiding the reflection from each line. The sampling clock will be delayed by internal circuit around 1 cycle. Thus, set the samplingclock as fast as possible. * Pin selection bit (PSEL) This bit is for selecting PS2 clock (CLK) or PS2 data (DAT) to connect to PS2Bi (i=0 to 2) .PS2Bi are external interrupt input pins. The bit setting definition is shown in table below.
Pin selection bit "0" "1"
PS2Bi (i= 0 to 2) PS2 clock (CLK) PS2 data (DAT)
* PS2 interface enable bit (PSEN) The PS2Ai (i= 0 to 2) and PS2Bi (i= 0 to 2) will be disconnected to hardware PS2 control section and become GPIO port when the bit is "0". The PS2Ai and PS2Bi will be connected to hardware PS2 control section when this bit is "1".
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PS2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol PS2MOD
Address 02AC16
Reset Value 0016
Bit Symbol
SCK0 SCK1 PSEL
Bit name
Sampling clock selection bits
Function
00 : Main clock /4 01 : Main clock /8 10 : Main clock /16 11 : Main clock /32
0 : PS2B connects to PS2 clock(CLK) 1 : PS2B connects to PS2 data(DAT)
RW
Pin selection bit
Nothing is assigned. Meaningless in writing, "0" in reading. PSEN0 PSEN1 PSEN2 PS2 interface enable bits 0 : P70,P73 as GPIO 1 : P70,P73 as PS2A0,PS2B0 0 : P71,P74 as GPIO 1 : P71,P74 as PS2A1,PS2B1 0 : P72,P75 as GPIO 1 : P72,P75 as PS2A2,PS2B2 Must be set to "0".
Reserved bit
Fig.GK-8 PS2 mode register
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(2) Operation description
q Basic setting The following items should be set for PS2 mode register (address 02AC16) set when PS2 interface is used. * PS2 interface enable bit Set the PS2 interface enable bits (bit4 to 6 of PS2 mode register) to "1" to enable the PS2 channels to be used. At this time PS2 clock goes "Low" (Receiving disable). * Sampling clock selection bit Sampling clock cycle (1/4,1/8,1/16,1/32 of main clock) is selected by setting sampling clock bit (bits 0,1). * External interrupt function support pin (PS2B) selection This bit is used to select PS2 clock (CLK) or PS2 data (DAT) for the external interrupt function support pin (PS2B).
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q Reception operation Fig.GK-9 shows the reception operation timing.
1
2
3
3
3
3
3
3
3
3
3
4
5
DAT CLK (Device side CLK) (Controller side CLK) Reception enable bit Data receiving flag Reception abort incognizable flag Transfer completion flag Interrupt request
start
D0
D1
D2
D3
D4
D5
D6
D7
parity stop
Fig.GK-9 Reception operation timing (1) Reception enable The reception operation is enabled by writing 0116 (reception enable bit = "1") to PS2i control register (address : 02A216, 02A616, 02AA16). The PS2 clock (CLK) will become "H". (2) Reception start The reception operation starts when both PS2 clock (CLK) and PS2 data (DAT) are detected with "L". (3) Data reception (The reception of data and parity bits) The content PS2 data (DAT) is read into PS2i shift register (address : 02A016, 02A416, 02A816) sequentially by the falling edge of PS2 clock (CLK). The data transfer sequence is data bit (D0 -D7) then parity bit. (4) Reception completion (Stop bit Reception completion) By detecting the falling edge of PS2 clock (CLK), the transfer completion flag (bit 0 of PS2i status register) is set to "1" after the update of error flag (bit 4 - 6 of PS2i status register) and the reception enable bit (bit 0 of PS2i control register) is cleared to "0". The PS2 clock (CLK) becomes "L" (reception disable status) and interrupt request occurs. (5) Data read out Read out data from PS2i shift register (address : 02A016,02A416,02A816). At this time , the error flags (Bit4 to 6) of and transfer completion flag (bit 0) of PS2i status register (address: 02A116, 02A516, 02A916) will be cleared to "0".
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q Transmission operation Fig.GK-10 shows the transmission operation timing.
1
2
3
3
3
3
3
3
3
3
3
3
4
5
6
DAT (Device side DAT) (Controller side DAT) CLK (Device side CLK) (Controller side CLK) Transmission enable flag Transfer completion flag Interrupt request
start
D0
D1
D2
D3
D4
D5
D6
D7
parity stop
ack
start
D0
D1
D2
D3
D4
D5
D6
D7
parity stop
Fig.GK-10 Transmission operation timing (1) Data writing Write transmission data to PS2i shift register (address : 02A016, 02A416, 02A816). At this time,PS2 data will become "L" (transmission start). (2) Transmission enable Set 0216 (Transmission enable bit = "1") to PS2i control register (address : 02A216, 02A616, 02AA16) for enabling transmission operation. At this time , PS2 clock (CLK) will become "H". (3) Data transmission (The transmission of data, parity and stop bits) The content of PS2i shift register (address : 02A016, 02A416, 02A816) will be output to the PS2 data (DAT) sequentially by the falling edge of PS2 clock (CLK). The sequence of data transfer is data bits (D0 to D7) , Parity bit, and stop bit. (4) Acknowledge reception The content of acknowledge bit will be read by the falling edge of PS2 clock (CLK). (5) Communication completion The communication opeartion is completed by detecting "H" on both PS2 clock (CLK) and PS2 data (DAT). After the update of error flag (bit 4 - 6 of PS2i status register), the transfer completion flag (bit 0 of PS2i status register) is set to "1" and the reception enable bit (bit 0 of PS2i control register) is cleared to "0". At this time, PS2 clock (CLK) becomes "L" (reception disable status) and the interrupt request occurs. (6) Status clear Read out the data from PS2i shift register (address : 02A016, 02A416, 02A816). At this time , the error flags (bits 4 to 6) and transfer completion flag (Bit0) of PS2i status register (address : 02A116, 02A516, 02A916) will be cleared to "0".
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q Transfer abort operation Fig.GK-11 shows the transfer abort operation timing.
1
2
3
3
3
3
45
6
DAT CLK (Device side CLK) (Controller side CLK) Transfer abort request bit Reception abort incognizable flag Transfer abort completion flag Transfer completion flag Interrupt request
start
D0
D1
D2
D3
D4
Fig.GK-11 Transfer abort operation timing ( reception)
(1) - (3) Data reception operation (4) Transfer abort request Set 0416 (transfer abort request bit = "1") to PS2i control register (address : 02A216, 02A616,02AA16). (5) Transfer abort completion The transfer abort completion flag (bit 6) and transfer completion flag (bit 0) of PS2i status register (address : 02A116, 02A516, 02A916) are set to "1", transfer abort request bit (bit 2) of PS2i control register (address : 02A216, 02A616, 02AA16) is cleared to "0". At this time, PS2 clock (CLK) becomes "L" (reception disable status) and interrupt request occurs. (6) Status clear By a pseudo read of PS2i shift register (address : 02A016, 02A416, 02A816), the transfer abort completion flag (bit 6) and transfer completion flag (bit 0) of PS2i status register (address : 02A116, 02A516, 02A916) are cleared to "0". Note: Do not execute the following transmission/reception during the period between the "L" output from PS2 clock (CLK) and the transfer abort request recognition of the device.
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M16C/6K9 Group
Port
Programmable I/O Ports
There are 129 programmable I/O ports: P0 to P16 (excluding P85). Each port can be set independently for input or output using the direction register. Pull-up resistances can be set in 4-port unit. (except for P10 and P14). The N channel open drain ports P60 to P63, P70 to P77, P80 to P84, P130 to P137 and P85 (input only port) do not build internal pull-up resistance. Fig.UA-1 to UA-6 show the configurations of programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Fig.UA-7 shows the configurations of direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P85.
(2) Port registers
Fig.UA-8 shows the configurations of port registers. These registers are used to write and read data for input and output to and from exterior. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Fig.UA-9 and UA-10, UA-11 shows the configurations of pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports (except for P10 and P14). When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. Pull-up resistance can be set to each pin of P10 and P14.
(4) Port control register
Fig.UA-12 shows the configurations of port control register 0, 1. Fig.UA-13 shows the configuraitons of port control register 2, 3. The bit 0 of port control register 0 is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. (neither input port nor output port)
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Port
The P0, P1, P40 to P46, P11 and P14 output type, CMOS or N channel open drain, are set by bit 0 to 6 of port control register 1 and bit 0 to 2 of port control register 3. 0 : CMOS output 1 : N channel open drain output Exception: P42 output type is N channel open drain if either bit 4 of port control register 1 or bit 2 of port control register 3 is set to "1". Bit 7 of port control register1 functions as below 0 : P40/P43 output is cleared by software only 1 : P40/P43 output is cleared by software or when output buffer 0 is read by host side. The driving ability of N channel output transistors for P140 to P143 can be selected by bit 6 of port control register 2 controls as below: 0 : Driving ability of N channel open drain output transistor is LOW 1 : Driving ability of N channel open drain output transistor is HIGH
(5) Port P4/P7 input register
Fig.UA-14 shows the configurations of P4 and P7 input register. By reading the registers, the input level of the corresponding pins can be known regardless the input/output mode.These two registers can be read regardless port direction setting. And the ports level will be read out. Port4 : Bit 0 to bit6's level will be read out. And bit7 is always "0". Port7 : Bit 0 to bit5's level will be read out. And bit6,7 is always "0".
(6) Port function selection register 0,1,2
Fig.UA-15, UA-16 shows the configurations of port function selection register 0,1,2. The port functions of ________ UART0 to UART2 input/output, TimerA0 to TimerA2 output, TimerB3,B4 input or external interrupt INT6 to __________ INT12 input can be switched by setting these two registers. By setting bit0,1 of port function selection register 2, the same frequency clock with f(XIN) can be output from P110 and P111.
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M16C/6K9 Group
Port
Pull-up selection
P00 to P07 P110 to P117
Direction register
Output formality selection bit Data bus Port latch (Note)
Pull-up selection
P12, P16 P140 to P147
Direction register
Output formality selection bit Data bus Port latch (Note)
Input respective peripheral function
Pull-up selection
P13, P43 to P46
Direction register "1"
Output formality selection bit Data bus Port latch
Output (Note)
Pull-up selection
P10, P11, P14, P15, P17 P40 to P42
Direction register "1"
Output formality selection bit Data bus Port latch
Output (Note)
Input respective peripheral function
(Note)
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc each port.
Fig.UA-1 Programmable I/O ports (1)
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M16C/6K9 Group
Port
Pull-up selection
P126, P127 P153 to P157
Direction register
Data bus
Port latch (Note)
Pull-up selection
P21, P24 to P27, P50 to P57 P91, P97 P120 to P125 P160, P161
Data bus
Direction register
Port latch (Note)
Input to respective peripheral function
Pull-up selection
P47
Direction register "1"
Output Data bus Port latch (Note)
Pull-up selection
P20, P22, P23, P30 to P37 P150 to P152, P64 to P67, P90, P92
Direction register "1"
Output Data bus Port latch (Note)
Input to respective peripheral function
Note.
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Fig.UA-2 Programmable I/O ports (2)
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M16C/6K9 Group
Port
P130 to P137
Direction register
Data bus
Port latch
(Note)
P76 to P77, P80 to P84
Direction register
Data bus
Port latch
(Note)
Input to respective peripheral function
P60 to P63, P70 to P75
Direction register "1"
Output Data bus Port latch
(Note)
Input to respective peripheral function
Note.
symbolizes a parasitic diode.
Fig.UA-3 Programmable I/O ports (3)
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M16C/6K9 Group
Port
Pull-up selection
Direction register
P100, P101 (Excepting the short dashes line section) P102 to P107 (Including the short dashes line section)
Data bus
Port latch (Note)
Analog input Input to respective peripheral function
P102 to P107 only
Pull-up selection DA output enable Direction register "1"
P93, P94
Output Data bus Port latch
(Note)
Input to respective peripheral function Analog output DA output enable
Pull-up selection
P95
Direction register "1"
Output Data bus Port latch
(Note)
Input to respective peripheral function Analog input
Pull-up selection
P96
Direction register "1"
Output Data bus Port latch (Note)
Analog input
Note
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Fig.UA-4 Programmable I/O ports (4)
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M16C/6K9 Group
Port
Pull-up selection
P87
Direction register
Data bus
Port latch (Note) fc
Input to respective peripheral function
Rf
Pull-up selection Rd Direction register
P86
"1"
Output Data bus Port latch (Note)
Note
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Fig.UA-5 Programmable I/O ports (5)
M1 M1 signal input (Note1)
M0 M0 signal input (Note1)
RESET RESET signal input (Note1)
Note1.
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin.
Fig.UA-6 I/O pins
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M16C/6K9 Group
Port
Port Pi direction register
b 7 b6 b 5 b 4 b3 b 2 b 1 b0
Symbol PDi(i=0-15, except 8)
Address 03E216,03E316,03E616,03E716,03EA16 03EB16,03EE16,03EF16,03F316,03F616 02E216,02E316,02E616,02E716,02EA16
When reset 0016
Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Bit name
Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register
Function
0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port) (i=0-15, except 8)
RW
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD8
Address 03F216
When reset 00X000002
Bit symbol
PD8_0 PD8_1 PD8_2 PD8_3 PD8_4
Bit name
Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Port P84 direction register
Function
0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port)
RW
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
PD8_6 PD8_7
Port P86 direction register Port P87 direction register
0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port)
Port P16 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD16
Address 02EB16
When reset XXXXXX002
Bit symbol
PD16_0
Bit name
Port P160 direction register
Function
0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port)
RW
PD16_1
Port P161 direction register
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
Fig.UA-7 Direction register
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M16C/6K9 Group
Port
Port Pi register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Pi(i=0 to15, except 8)
Address 03E016,03E116,03E416,03E516,03E816 03E916,03EC16,03ED16,03F116,03F416 02E016,02E116,02E416,02E516,02E816
When reset Indeterminate
Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Bit name
Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (i=0-15, except 8)
RW
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P8
Address 03F016
When reset Indeterminate
Bit symbol
P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7
Bit name
Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : "L" level data 1 : "H" level data
RW
Port P16 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P16
Address 02E916
When reset Indeterminate
Bit symbol
PD16_0
Bit name
Port P160 register
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data
RW
PD16_1
Port P161register
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
Fig.UA-8 Port register
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M16C/6K9 Group
Port
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0
Address 03FC16
When reset 0016
Bit symbol
PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07
Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up
Function
The corresponding port is pulled high with a pull-up resistor 0: Not pulled high 1: Pulled high
RW
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1
Address 03FD16
When reset 0016
Bit symbol
PU10 PU11 PU12 PU13
Bit name
P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 to P57 pull-up
Function
The corresponding port is pulled high with a pull-up resistor 0: Not pulled high 1: Pulled high
RW
Nothing is assigned. (Note) Can't write to this bit. The value, if read, turns out to be "0". PU15 P64 to P67 pull-up
Nothing is assigned. (Note) Can't write to this bit. The value, if read, turns out to be "0". Note.Since P60 to P63 and P70 to P77 are N-channel open drain ports, internal pull-up is not available for them.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2
Address 03FE16
When reset 0016
Bit symbol
Bit name
Function
RW
Nothing is assigned. (Note) Can't write to this bit. The value, if read, turns out to be "0". PU21 PU22 PU23 P86, P87 pull-up(Note) P90 to P93 pull-up P94 to P97 pull-up The corresponding port is pulled high with a pull-up resistor 0: Not pulled high 1: Pulled high
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0". Note.Since P80 to P84 are N-channel open drain ports, internal pull-up is not available for them. And P85 is input port only , also no internal pull-up is available.
Fig.UA-9 Pull-up control register(1)
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M16C/6K9 Group
Port
Pull-up control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR3
Address 02FC16
When reset 0016
Bit symbol
PU30 PU31 PU32 PU33
Bit name
P110 to P113 pull-up P114 to P117 pull-up P120 to P123 pull-up P124 to P127 pull-up
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Pull-up control register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR4
Address 02FD16
When reset 0016
Bit symbol
PU40 PU41 PU42
Bit name
P150 to P153 pull-up P154 to P157 pull-up P160, P161 pull-up
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Fig.UA-10 Pull-up control register(2)
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M16C/6K9 Group
Port
Pull-up control register 5
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR5
Address 02F216
When reset 0016
Bit symbol
PU50 PU51 PU52 PU53 PU54 PU55 PU56 PU57
Bit name
P100 pull-up P101 pull-up P102 pull-up P103 pull-up P104 pull-up P105 pull-up P106 pull-up P107 pull-up
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Pull-up control register 6
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR6
Address 02F316
When reset 0016
Bit symbol
PU60 PU61 PU62 PU63 PU64 PU65 PU66 PU67
Bit name
P140 pull-up P141 pull-up P142 pull-up P143 pull-up P144 pull-up P145 pull-up P146 pull-up P147 pull-up
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Fig.UA-11 Pull-up control register(3)
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M16C/6K9 Group
Port
Port control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PCR0
Address 03FF16
When reset 0016
Bit Symbol
PCR00
Bit name
Port P1 control register
Function
0 : When input port, read port input level. When output port, read the contents of port P1 register 1 : Read the contents of port P1 register though input/output port.
RW
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Port control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PCR1
Address 02FE16
When reset 0016
Bit Symbol
PCR10 PCR11 PCR12 PCR13 PCR14 PCR15 PCR16 PCR17
Bit name
Output type selection bit (P00 to P03) Output type selection bit (P04 to P07) Output type selection bit (P10 to P13) Output type selection bit (P14 to P17) Output type selection bit (P40 to P46) Output type selection bit (P110 to P113) Output type selection bit (P114 to P117) P40,P43 output clear function selection bit
Function
0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : Cleared by software only 1 : Cleared by software or when output buffer is read by host side.
RW
Fig.UA-12 Port control register 0, 1
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M16C/6K9 Group
Port
Port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol PCR2
Address 02FF16
When reset 0016
Bit symbol
Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit PCR26
Bit name
Function
Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0"
RW
Drive polarity selection bit (P140 to P143)
0 : Low side 1 : High side
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Port control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PCR3
Address 02F716
When reset 0016
Bit symbol
PCR30 PCR31 PCR32
Bit name
Output type selection bit (P140 to P143) Output type selection bit (P144 to P147) Output type selection bit (P42)
Function
0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain
RW
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Fig.UA-13 Port control register 2, 3
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M16C/6K9 Group
Port
Port P4 input register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P4PIN
Address 02FA16
When reset 0XXXXXXX2
Bit Symbol
P4PIN_0 P4PIN_1 P4PIN_2 P4PIN_3 P4PIN_4 P4PIN_5 P4PIN_6
Bit name
Port P40 input register Port P41 input register Port P42 input register Port P43 input register Port P44 input register Port P45 input register Port P46 input register
Function
For reading P40 pin level For reading P41 pin level For reading P42 pin level For reading P43 pin level For reading P44 pin level For reading P45 pin level For reading P46 pin level
RW
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Port P7 input register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P7PIN
Address 02FB16
When reset 00XXXXXX2
Bit Symbol
P7PIN_0 P7PIN_1 P7PIN_2 P7PIN_3 P7PIN_4 P7PIN_5
Bit name
Port P70 input register Port P71 input register Port P72 input register Port P73 input register Port P74 input register Port P75 input register
Function
For reading P70 pin level For reading P71 pin level For reading P72 pin level For reading P73 pin level For reading P74 pin level For reading P75 pin level
RW
Nothing is assigned. Can't write to this bit. The value, if read, turns out to be "0".
Fig.UA-14 Port P4,P7 input register
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M16C/6K9 Group
Port
Port function selection register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL0
Address 02F816
When reset 0016
Bit Symbol
PSL00
Bit name
UART0 I/O pin selection bit
Function
0 : P60 to P63 1 : P10 to P13 0 : P64 to P67 1 : P14 to P17 0 : P70 to P73 1 : P20 to P23 0 : P103 1 : P14 0 : P104 1 : P15 0 : P105 1 : P16 0 : P106 1 : P17 0 : f(XIN) 1 : fC
RW
PSL01
UART1 I/O pin selection bit
PSL02
UART2 I/O pin selection bit
PSL03 PSL04
INT7 input pin selection bit INT8 I/O pin selection bit
PSL05
INT9 I/O pin selection bit
PSL06
INT10 I/O pin selection bit
PSL07 (Note)
P110 output clock selection bit
Note. Enabled only if bit 0 of port function selection register 2 is set to "1". If fc is selected, the phase of output clock is reversed to XCIN.
Port function selection register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL1
Address 02F916
When reset 0016
Bit Symbol
PSL10
Bit name
TA0 output pin selection bit 0 : P40 1 : P150 0 : P41 1 : P151 0 : P42 1 : P152 0 : P93 1 : P160 0 : P94 1 : P161
Function
RW
PSL11
TA1 output pin selection bit
PSL12
TA2 output pin selection bit
PSL13
TB3 output pin selection bit
PSL14
TB4 output pin selection bit
PSL15 (Note)
INT6-INT11 input pin switching bit
0 : P97, P103 to P107 1 : P120, P121 to P125
Nothing is assigned. Meaningless in writing, "0" in reading. Note. If this is set to "1" then port function selection register 1 (address 02F816) bit 3 to bit6 setting will be ignored.
Fig.UA-15 Port function selection register 0,1
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M16C/6K9 Group
Port
Port function selection register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL2
Address 02F116
When reset 0016
Bit Symbol
PSL20
Bit name
P110 : f1 output function selection bit
Function
0 : P110 as GPIO 1 : P110 as f1 output 0 : P111 as GPIO 1 : P111 as f1 output 0 : P90 to P92 1 : P150 to P152 0 : P95 to P97 1 : P155 to P157
RW
PSL21 PSL22
P111 : f1 output function selection bit
S I/O3 I/O pin selection bit
PSL23
S I/O4 I/O pin selection bit
Nothing is assigned. Meaningless in writing, "0" in reading.
Fig.UA-16 Port function selection register 2
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M16C/6K9 Group
Port
Table.UA-1 Example connection of unused pins in single-chip mode
Pin name Ports P0 to P10 (excluding P85) Ports P11 to P16 XOUT (Note) NMI FVCC AVCC AVSS, VREF, M1 Connection After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. Open Connect via resistor to VCC (pull-up) Apply 0V to 3.6V Connect to VCC Connect to VSS
Note: With external clock input to XIN pin.
Microcomputer Port P0 to P16 (input mode) (except for P85)
(input mode) (output mode)
open
NMI XOUT open VCC AVCC 0.47 mF M1 AVSS VREF M0 VSS In single-chip mode
Fig.UA-17 Example connection of unused pins
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M16C/6K9 Group
Usage precaution
Usage Precaution Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. But, reading the timer Ai register with the reload timing gets "FFFF16". Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a setting value to the timer.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. But, reading the timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a setting value to the timer. (2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to "0" while a count is in progress causes as follows: * The counter stops counting and a content of reload register is reloaded. * The TAiOUT pin outputs "L" level. * The interrupt request generated and the timer Ai interrupt request bit goes to "1". (2) The timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: * Selecting one-shot timer mode after reset. * Changing operation mode from timer mode to one-shot timer mode. * Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. (2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes "1".
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M16C/6K9 Group
Usage precaution
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. But, reading the timer Bi register with the reload timing gets "FFFF16". Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a setting value to the timer.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to "1". (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an elapse of 1 s or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to "1".
Interrupts
(1) Reading address 0000016 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.
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(2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. _______ When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first _______ instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ * As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor (pull-up) if unused. Be sure to work on it. _______ * Do not get either into stop mode with the NMI pin set to "L". (4) External interrupt _______ _________ * When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
* When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Noise (1) Insert the by-pass condencer to the Vcc-Vss line for preventing a noise and latch-up. Connect the by -pass condencer (about 0.1F) between Vcc pin and Vss pin. It is distance must be shortest rather sicker line.
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DMAC
The write to DMAC bit of DMAiCON register (i= 0-1) If (a) conditions are matched, follow (b) as wirte procedure. (a) Conditions Write "1" to DMAE bit again when DMAE bit is "1" (DMAi active status). The possibility that the write to DMAE bit and DMA request occur at the same time. . (b) Write procedure (1) Write "1" to both DMAE bit and DMAS bit at the same time (Note 1). (2)Confirm with program that DMAi is at initial condition (Note 2). Note 1: The DMAS will be "0" if writing "0" to it. However, there is no change if writing "1" to the bit. Hence, if "1" is to be written to DMAE by writing DMAiCON register, setting the value of DMAS to "1", DMAS will remain the same status before the writing. If read modify write command is used to write to DMAE bit, setting the value of DMAS to "1", the DMA request will be retained during the execution of the command. Note 2: Comfirm it with TCRi register. If the value read from TCRi register becomes the same with that, which was written to TCRi register before the start of DMA transfer (the TCRi value will be 1 decremented after writing to DMAE bit), it is at initial condition. Otherwise, DMA is still under transfer.
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Electrical characteristics
Table.ZA-1 Absolute maximum ratings
Symbol Vcc AVcc FVcc Supply voltage Analog Supply voltage Supply voltage for program/erase Input voltage VI RESET,M0,M1,VREF,XIN, P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P64 to P67,P86,P87, P90 to P97,P100 to P107,P110 to P117, P120 to P127,P140 to P147,P150 to P157, P160,P161 P60 to P63,P70 to P77,P80 to P84,P85, P130 to P137 output voltage VO P00 to P07,P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P64 to P67,P86,P87, P90 to P97,P100 to P107,P110 to P117, P120 to P127,P140 to P147,P150 to P157, P160,P161,XOUT P60 to P63,P70 to P77,P80 to P84, P130 to P137 Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature Ta=25 C Parameter Condition VCC=AVCC VCC=AVCC Rated value -0.3 to 4.6 -0.3 to 4.6 -0.3 to 4.6 Unit V V V
-0.3 to Vcc+0.3
V
-0.3 to 5.8
V
-0.3 to Vcc+0.3
V
-0.3 to 5.8 300 -20 to 85 -40 to 125
V mW C C
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Table.ZA-2 Recommended operating conditions (referenced to Vcc=3.0V to 3.6V,Ta= -20 to 85oC)
Symbol Vcc AVcc FVcc Vss AVss Supply voltage Analog Supply voltage Supply voltage for program/erase Supply voltage Analog Supply voltage "H" input voltage VIH P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47, P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107, P110 to P117, P120 to P127,P140 to P147, P150 to P157, P160,P161,XIN, RESET, M0,M1 P60 to P63, P70 to P77,P80 to P84,P85,P130 to P137, PSA0 to PSA2, PSB0 to PSB2 LAD0 to LAD3,LFRAME,LCLK,SERIRQ,CLKRUN SDA0,SCL0,SDA1,SCL1,SDA2,SCL2 P60 to P63,P76,P77,P81 to P84 "L" input voltage VIL
I2C-BUS input level selected SMBUS input level selected
Parameter Min. 3.0 During flash memory read During program/erase 0 3.0
Standard Typ. 3.3 Vcc
Unit Max. 3.6 3.6 3.6 V V V V V V Vcc V
0 0 0.8Vcc
0.8Vcc 0.6Vcc 0.7Vcc 1.4 0
5.5 Vcc 5.5 5.5 0.2Vcc
V V V V
P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47, P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107, P110 to P117, P120 to P127,P140 to P147, P150 to P157, P160,P161,XIN, RESET, M0,M1 P60 to P63, P70 to P77,P80 to P84,P85,P130 to P137, PSA0 to PSA2, PSB0 to PSB2 LAD0 to LAD3,LFRAME,LCLK,SERIRQ,CLKRUN SDA0,SCL0,SDA1,SCL1,SDA2,SCL2 P60 to P63,P76,P77,P81 to P84
I2C-BUSes input level selected SMBUS input level selected
V
0 0 0 0
0.2Vcc 0.2Vcc 0.3Vcc 0.6
V V V V
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Table.ZA-3 Recommended operating conditions (referenced to Vcc=3.0V to 3.6V,Ta= -20 to 85oC)
Symbol I OH (peak) "H"peak output current Parameter P00 to P07, P10 to P17,P20 to P27,P30 to P37,P40 to P47, P50 to P57,P64 to P67,P86 to P87,P90 to P97,P100 to P107, P110 to P117, P120 to P127,P140 to P147,P150 to P157, P160,P161 P00 to P07, P10 to P17,P30 to P37,P40 to P47, P50 to P57,P60 to P67,P76 to P77,P80 to P84, P86 to P87, P90 to P97,P100 to P107, P110 to P117,P120 to P127, P130 to P137,P144 to P147, P150 to P157,P160,P161 P20 to P27 I OL (peak) I OH (avg) "L"peak output current P140 to P143 Driven ability:High Driven ability:Low Min. Standard Typ. Max. -10.0 Unit
mA
I OL (peak)
"L"peak output current
10.0 20.0 20.0 10.0 -5.0
mA mA mA mA mA
"H" average output P00 to P07, P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P86 to P87,P90 to P97, current P100 to P107, P110 to P117, P120 to P127,P140 to P147, P150 to P157,P160,P161 "L"average output current P00 to P07, P10 to P17,P30 to P37, P40 to P47, P50 to P57,P60 to P67,P76 to P77,P80 to P84, P86 to P87, P90 to P97,P100 to P107,P110 to P117,P120 to P127, P130 to P137,P140 to P147,P150 to P157,P160,P161 P20 to P27 Driven ability:High "L"average output P140 to P143 Driven ability:Low current 0
I OL (avg)
5.0 15.0 15.0 5.0 16 50
mA mA mA mA MHz kHz
I OL (avg) f (XIN) f (XcIN)
Main clock input oscillation frequency Subclock oscillation frequency
32.768
Note1 : The average output current is the average value during the 100ms period limited current. Note2 : The value are as follow: The sum of IOL (peak) of P0,P1,P2,P86 to P87,P9,P10,P11,P120 to P126,P153 to P157 P16 should be under 80mA. The sum of IOH (peak) of P0,P1,P2,P86 to P87,P9,P10,P11,P120 to P126,P153 to P157 P16 should be under 80mA. The sum of IOL (peak) of P3,P4,P5,P6,P7,P80 to P84,P13,P14,P150 to P152 should be under 80mA. The sum of IOH (peak) of P3,P4,P5,P64 to P67,P14,P150 to P152 should be under 80mA.
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Table.ZA-4 Electrical characteristics (referenced to Vcc=3.0V, Vss=0V, Ta=25oC, f(XIN)=16MHz with 0 wait unless otherwise specified)
Symbol VOH High output voltage Parameter P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P86, P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P140 to P147, P150 to P157, P160, P161 XOUT HIGH POWER LOWPOWER HIGHPOWER XCOUT LOWPOWER P00 to P07, P10 to P17, P30 to P37, P40 to P47,P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160, P161 P20 to P27 P140 to P143 HIGH POWER LOWPOWER XOUT HIGH POWER LOWPOWER HIGHPOWER XCOUT LOWPOWER _______ _________ TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT11, __________ ________ ________ ________ ADTRG, CTS0, CTS1, CTS2, CLK0, CLK1, CLK2, CLK3, CLK4, SIN3, SIN4, RXD0, RXD1, _______ ________ ________ RXD2, ICCK, NMI, KI00 to KI07 ____________ RESET P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P120 to P127, P130 to P137, P140 to P147, ____________ P150 to P157, P160, P161, XIN, RESET, M0, M1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160, P161, ____________ XIN, RESET, M0, M1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P86, P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P140 to P147, P150 to P157, P160, P161 XIN XCIN When reset, the output pins are opened , the other pins are connected to Vss. When clock is stopped f(XIN)=16MHZ, Square wave without division f(XCIN)=32kHZ, Square wave When operation under RAM f(XCIN)=32kHZ, Square wave When operation under Flash memory f(XCIN)=32kHZ, With WAIT oscillation capacity High (Note1) f(XCIN)=32kHZ, With WAIT oscillation capacity Low (Note1) Ta=25C When clock is stopped Ta=85C When clock is stopped 2.0 16.0 35.0 450.0 24.0 Measuring condition IOH=-1mA Min. 2.5 Standard Typ. Max. V Unit
VOH
VOL
High output voltage High output voltage Low output voltage
IOH= -0.1mA IOH= -50A With no load applied With no load applied
2.5 2.5 3.0 1.6
V V
IOL=1mA
0.5
V
VOL VOL
VT+VT-
Low output voltage Low output voltage Low output voltage Hysteresis
VCC=3V, IOL=3mA IOL=3mA IOL=1mA IOH=0.1mA IOH=50A With no load applied With no load applied 0.2
0.5 0.5 0.5 0.5 0.5 0 0 0.8
V V V V
V
VT+VTIIH
Hysteresis HIGH input current
0.2
1.8
V
VI=3V
4.0
A
IIL
Low input current
VI=0V
-4.0
A
R PULLUP
Pull-up resistance
VI=0V
66.0
120.0
500.0
k
R fXIN R fXCIN V RAM I CC
Feedback resistance Feedback resistance RAM retention voltage Power supply current
3.0 10.0
M M V mA A A
4.5
A
2.5
A
100.0 300.0
A A
Note1 : Under the state that a timer is operating with fc32.
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Table.ZA-5 DC characteristics (referenced to Vcc=3.0 to 3.6V, Ta=25oC unless otherwise specified)
Standard (Typ.) Symbol Ipp Parameter FVcc power current Measuring condition FVcc=3.0 to 3.6V Program
60mA
Erase
30mA
Table.ZA-6 A-D conversion characteristics (referenced to Vcc=AVcc=VREF=3V,Vss=AVss=0V at Ta=25oC unless otherwise specified)
Symbol Resolution Absolute accuracy RLADDER tCONV VREF VIA Ladder resistance Conversion time Reference voltage Analog input voltage 8 bit 10 bit 8 bit 10 bit Parameter Measuring condition VREF =VCC VREF =VCC=3V, OAD=fAD VREF =VCC 10 6.125 7.375 2.7 0 VCC VREF Min. Standard Typ. Max. 10 2 6 40 Unit Bits LSB LSB kW ms ms V V
Table.ZA-7 D-A conversion characteristics (referenced to Vcc=AVcc=VREF=3V,Vss=AVss=0V at Ta=25oC unless otherwise specified)
Symbol tsu RO IVREF Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition Min. Standard Typ. Max. 8 1.0 3 4 20 10 1.0 Unit Bits % ms kW mA
(Note1)
Note1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. When the content of D-A register is not "00", the IVREF will also be sent even if VREF is disconnected.
Table.ZA-8 Comparator characteristics (referenced to Vcc=AVcc=VREF=3V to 3.6V,Vss=AVss=0V at Ta=25oC)
Symbol TCONV VIA IIA RLADDER Parameter Resolution Absolute accuracy Conversion time Analog input voltage Analog input current Ladder resistance when f(XIN) = 16MHz when f(XIN) = 8MHz Measuring condition Min. Standard Typ. Max. 4 1/2 1.75 3.5 VCC 0 5.0 50 20 40 Unit Bits LSB ms ms V ms kW
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Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified) Table.ZA-9 External clock input
Symbol
tc tw(H) tw(L) tr tf
Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rising time External clock falling time
Standard Min.
62.5 25 25 9 9
Max.
Unit
ns ns ns ns ns
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Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified) Table.ZA-10 Timer A input (The count input of event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input "H" pulse width TAiIN input "L" pulse width Parameter Standard Min. 150 60 60 Max. Unit ns ns ns
Table.ZA-11 Timer A input (The gating input of timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input "H" pulse width TAiIN input "L" pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns
Table.ZA-12 Timer A input (The external trigger input of one shot timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input "H" pulse width TAiIN input "L" pulse width Parameter Standard Min. 300 150 150 Max. Unit ns ns ns
Table.ZA-13 Timer A input (The external trigger input of pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input "H" pulse width TAiIN input "L" pulse width Parameter Standard Min. 150 150 Max. Unit ns ns
Table.ZA-14 Timer A input (The up down input of event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input "H" pulse width TAiOUT input "L" pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. 3000 1500 1500 600 600 Max. Unit ns ns ns ns ns
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Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified) Table.ZA-15 Timer B input (The count input of event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (single edge count) TBiIN input "H" pulse width (single edge count) TBiIN input "L" pulse width (single edge count) TBiIN input cycle time (double edge count) TBiIN input "H" pulse width (double edge count) TBiIN input "L" pulse width (double edge count) Standard Min. 150 60 60 300 160 160 Max. Unit ns ns ns ns ns ns
Table.ZA-16 Timer B input (Pulse period measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input "H" pulse width TBiIN input "L" pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns
Table.ZA-17 Timer B input (Pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input "H" pulse width TBiIN input "L" pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns
Table.ZA-18 A-D trigger input
Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (The Min. of trigger) ADTRG input "L" pulse width Standard Min. 1500 200 Max. Unit ns ns
Table.ZA-19 Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input "H" pulse width CLKi input "L" pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
______
Parameter
Standard Min. 300 150 150 160 0 50 90 Max.
Unit ns ns ns ns ns ns ns
Table.ZA-20 External interrupt INTi input
Symbol tw(INH) tw(INL) INTi input "H" pulse width INTi input "L" pulse width Parameter Standard Min. 380 380 Max. Unit ns ns
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Timing requirements (referenced to Vcc = 3.0 to 3.6V, Vss = 0V, Ta =25 C) Table. ZA-21 Multi-master I2C-BUS line
Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tsu;DAT tsu;STA tsu;STO Bus free time The hold time in start condition The hold time in SCL clock "0" status SCL, SDA signals' rising time Data hold time The hold time in SCL clock "1" status SCL, SDA signals' falling time Data setup time The setup time in restart condition Stop condition setup time Parameter Standard clock mode Min. Max. 4.7 4.0 4.7 1000 0 4.0 300 250 4.7 4.0 High-speed clock mode Min. Max. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 0.9 300 Unit s s s ns s s ns ns s s
Table. ZA-22 PS2 interface (referenced to Vcc = 3.0 to 3.6V, Vss = 0V, Ta =25 C)
Symbol twL twH tsu th td tv PS2 clock "L" pulse width PS2 clock "H" pulse width PS2 data setup time PS2 data hold time PS2 data delay time PS2 data valid time Parameter Min. 30 30 5 0 0 twL-5 twL-5 Standard Typ. Max. 50 50 Unit s s s ns s s
Table. ZA-23 LPC bus interface/serial interrupt output
Symbol tC(CLK) tWH(CLK) tWL(CLK) tsu(D-C) th(C-D) tV(C-D) toff(A-F) Parameter LCLK clock input cycle time LCLK clock input "H" pulse width LCLK clock input "L" pulse width
_______________ _______________
Standard Min. 30 11 11 7 0 2 11 28 Typ. Max.
Unit ns ns ns ns ns ns ns
LAD3-LAD0,SERIRQ,CLKRUN,LFRAME Input setup time
_______________ _______________
LAD3-LAD0,SERIRQ,CLKRUN , LFRAME input hold time
_______________ _______________
LAD3-LAD0,SERIRQ,CLKRUN , LFRAME valid delay time
_______________
LAD3-LAD0,SERIRQ,CLKRUN floating output delay time
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Timing
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
30pF
Fig.ZA-1 The measuring circuit for port 0 to port 16
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tc(TA) tw(TAH) TAiIN input tw(TAL)
tc(UP) tw(UPH) TAiOUT input tw(UPL)
TAiOUT input (Up down input) Inevent counter mode TAiIN input (when selecting the fulling edge count) TAiIN input (when selecting the rising edge count) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input th(TIN-UP) tsu(UP-TIN)
tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D)
Fig.ZA-2 Timing diagram (1)
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Timing
SDA
tBUF tLOW tR tF
Sr p
tHD:STA
tsu:STO
SCL
p
S
tHD:STA
tHD:DTA
tHIGH
tsu:DAT
tsu:STA
Fig.ZA-3 Timing diagram (2)
PS/2 interface timing diagram
In receiving
tWH tWL
0.8VCC 0.2VCC 0.2VCC
CLK
0.8VCC
tsu
0.8VCC
th
0.8VCC 0.2VCC
DATA
0.2VCC
In transmitting
tWL
0.8VCC
tWH
0.8VCC 0.2VCC
CLK
0.2VCC
0.2VCC
td
tv
0.8VCC 0.2VCC 0.8VCC 0.2VCC
DATA
Fig.ZA-4 Timing diagram (3)
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Timing
LPC bus interface/serial interrupt output timing
tC(CLK) tWH(CLK) VIH VIL tWL(CLK)
LCLK
tsu(D-C)
th(C-D)
LAD[3:0] SERIRQ,CLKRUN,LFRAME (Input)
tv(C-D)
LAD[3:0] SERIRQ,CLKRUN,LFRAME (Active output)
toff(A-F)
LAD[3:0] SERIRQ,CLKRUN,LFRAME (Floating output )
Fig.ZA-5 Timing diagram (4)
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M16C/6K9 Group
Flash memory version
Feature Outline
Table AB-1 shows the feature outline of M16C/6K9 (build-in NEW DINOR flash memory version). Table.AB-1 Feature outline of M16C/6K9 (build-in NEW DINOR flash memory version)
Item Power supply voltage Power supply voltage for program/erase Flash memory operation mode Erase block division Program method Erase method Program/ erase control method Number of command Program/ erase count ROM code protect User ROM area Boot ROM area Feature 3.0-3.6V (f(XIN)=16MHz, 0 wait) 3.0-3.6V (CPU reprogram mode, f(XIN)=8MHz with 0 wait or 16MHz with 1 wait) 3 modes (parallel I/O, standard serial I/O, CPU reprogram) See Fig.AB-1 1 division (4K bytes) (Note1) 2-byte unit Block erase Program/ erase controlled by s/w commands 5 commands 100 times Support for parallel I/O and standard serial I/O modes
Note1: The control program for standard serial I/O mode is stored in boot ROM area when shipping from factory. The area can only be erased or programmed by parallel I/O mode.
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M16C/6K9 Group
Flash memory version
Flash Memory
The M16C/6K9 (build-in flash memory version) contains the NEW DINOR type flash memory, which is applied 2 power supplies VCC=3.3V when using CPU reprogram or standard serial I/O mode. For the flash memory, 3 flash memory modes are available in which to read, program and erase. They are parallel I/O mode, standard serial I/O mode and CPU reprogram mode. For parallel I/O mode, a programmer is used. For standard serial I/O and CPU reprogram modes, the flash memory is manipulated by CPU. Each mode is detailed in the pages to follow. Fig. AB-1 shows that flash memory is divided into several blocks. Erasing is in block unit. In addition to the ordinary user ROM area there is a boot ROM area to store the control program for the CPU reprogram and standard serial I/O modes. The control program for standard serial I/O mode is stored in boot ROM area when shipping from factory. User can reprogram the program to suit its own application system. The area can only be erased or programmed by parallel I/O mode.
Chip name M306K9FCL M306K9F8L
The start address of the flash memory 0E000016 0F000016
0E000016 Block 3 : 32K bytes Block 6 : 64K bytes
0F000016 Block 5 : 32K bytes 0F800016 Block 4 : 8K bytes 0FA00016 Block 3 : 8K bytes 0FC00016 0FE00016 0FF00016 0FFFFF16 Block 2 : 8K bytes Block 1 : 4K bytes Block 0 : 4K bytes User block area 0FF00016 0FFFFF16 4K bytes Boot block area
Note 1: Boot ROM area can be reprogrammed only in parallel I/O mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum even address in the block.
Fig.AB-1 Block diagram of flash memory version
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M16C/6K9 Group
CPU Reprogram Mode
CPU reprogram mode
In CPU reprogram mode, the on-chip flash memory can be operated on (read, program or erase) under the control of CPU. In CPU reprogram mode, only the user ROM area shown in Fig.AB-1 can be reprogrammed. The boot ROM area cannot be reprogrammed. Make sure the program and block erase commands are issued only for each block of the user ROM area. The control program for CPU reprogram mode can be stored in either user ROM or boot ROM area. In CPU reprogram mode, because the flash memory cannot be read form CPU, the control program must be transferred to the RAM area before execution.
Microcomputer mode and Boot mode
The control program for CPU reprogram mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/ O mode becomes disable.) See Fig.AB-1 for details about the boot ROM area. Normal microcomputer mode is entered when reset with pulling "L" of M0. In this case, the CPU starts operating the control program in user ROM area. If the microcomputer is reset with M0 being "H" and M1 being "L", the CPU starts operating the control program in boot ROM area. This mode is called as "boot" mode.
Block address
Block address refers to the maximum even address of each block. The address is used in block erase command.
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M16C/6K9 Group
CPU Reprogram Mode
Feature Outline (CPU reprogram mode)
In CPU reprogram mode, the CPU erases, programs and reads the on-chip flash memory as instructed by S/W commands. The reprogram control program must be transferred to the RAM area before it can be executed. The CPU reprogram mode is accessed by writing "1" to the CPU reprogram select bit (bit 1 in address 03B716). S/W commands are accepted once the mode is accessed. In CPU reprogram mode, the writing and reading of the commands and data should be in even address ("0" for byte address A0) in 16-bit unit, so the 8-bit unit S/W commands should be written in even address. Commands are ignored with odd address. Use S/W commands to control flash memory programming and erasing. Whether the programming and erasing operation terminates correctly or in error can be verified by reading the status register. Fig.BB-1 shows the flash control register. _____ Bit 0 is the RY/BY status flag exclusively used to read the operating status of the flash memory. During programming and erasing operation, it is "0", otherwise it is "1". Bit 1 is the CPU reprogram mode select bit. When the bit is set to "1", CPU reprogram mode is entered S/W commands then can be accessed. In CPU reprogram mode, the CPU cannot access the on-chip flash memory directly. Therefore, use the control program in RAM to write the bit to "1". To set the bit, it is necessary to write "0" and then write "1" in succession. The bit can be cleared to "0" by only writing the "0". Bit 3 is the flash memory reset bit used to reset the control circuit of the on-chip flash memory. The bit is used when exiting the CPU reprogram mode and when flash memory access has failed. When the CPU reprogram mode select bit is "1", writing "1" to the bit resets the control circuit. To release the reset, it is necessary to set the bit to "0". If the control circuit is reset while erasing is in progress, the wait for 5 ms is needed so that the flash memory can restore to the normal operation. Bit 5 of the flash control register 0 is the user ROM select bit. It is enabled only in boot mode. When the bit is set to "1", the accessed area is switched from boot ROM to user ROM. When CPU reprogram mode is entered in boot mode, please set this bit to "1". The bit is disabled when program starts in user ROM. Please write the bit with the program that is not located in on-chip flash memory area. Fig.BB-2 shows a flowchart for the setting/ releasing the CPU reprogram mode.
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CPU Reprogram Mode
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR Bit symbol
Address
03B716
When reset
XX0000012
0
0
Bit name RY/BY signal status bit CPU reprogram mode select bit (Note 1)
Function 0: Busy (be written and erased) 1: Ready 0: Normal mode 1: CPU reprogram mode Must be "0". 0: Normal operation 1: Reset Must be "0".
RW RW
FMR0 FMR1
Reserved bit FMR3 Flash memory reset bit (Note 2)
Reserved bit FMR5
User ROM area select bit 0: Access to boot ROM area (Note 3) (Only enabled in boot mode) 1: Access to user ROM area
Nothing is assigned. When write, set "0". When read, value is indeterminate. Note 1: To write "1" to the bit, it is necessary to write "0" and "1" in succession. Otherwise the bit will not be "1". Please do not enter interrupt and DMA. Note 2: It is enabled only CPU reprogram mode select bit is "1". After setting to "1"(reset), please write "0" in succession. Note 3: Please write this bit with program that is not located in on-chip flash memory area.
Flash memory identification register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FTR
Address
03B416
When reset
XXXXXX102
Function
The value after reset XXXXXX102 : M16C/6K9 Group
RW
000000002 XXXX00012
: M16C/6K7 Group : M16C/6K5 Group (Note)
Note: Address 03B416 of M16C/6K5 Group is the flash memory control register.
Fig.BB-1 The structure of flash memory control register and flash memory identification register
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CPU Reprogram Mode
Program located in ROM
Program located in RAM
Start
*1
Single-chip mode or boot mode
(Only for boot mode) Set user ROM area select bit to "1"
Set processor mode register (Note 1)
Set CPU reprogram mode select bit="1" (write "0" and then write "1") (Note 2)
Transfer CPU reprogram mode control program to RAM area
Operate with S/W commands to erase and program.
Jump to the program that is transferred to RAM (the operation hereafter is on RAM)
Reset with read array command or the setting of the flash memory reset bit (write "1" and then write "0") (Note 3)
*1 Write "0" to CPU reprogram mode select bit.
(Only for boot mode) Write user ROM area select bit to "0". (Note 4)
End
Note 1: Set the main clock frequency as shown below using the main clock divide ratio select bits (bit 6 at address 000616 and bit 6 and 7 at address 000716): (1) Not exceeding 8 MHz if wait bit (bit 7 of address 000516) = "0". (No wait for internal accessing) (2) Not exceeding 16 MHz if wait bit (bit 7 of address 000516) = "1". (1 wait for internal accessing) Note 2: For writing "1" to the bit, it is necessary to write "0" and "1" in succession. Otherwise the bit will not be "1". Please do not enter interrupt and DAM. The write to the bit should be executed other than the flash memory area and the NMI pin should be in "H" state. Note 3: Be sure to execute a read command or to set flash memory reset bit before exiting the CPU reprogram mode after completing erasing or programming operation. Note 4: The bit can remain "1" too. If it is "1", user ROM area will be accessed.
Fig.BB-2 CPU reprogram mode set/reset flowchart
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M16C/6K9 Group
CPU Reprogram Mode
Precautions on CPU reprogram mode
Described below are the precautions to be observed in programming the flash memory in CPU reprogram mode. (1) Operation speed During CPU reprogram mode, set the main clock frequency as shown below using the main clock divide ratio select bits (bit 6 at address 000616 and bit 6 and 7 at address 000716): Not exceeding 8MHz if wait bit (bit 7 of address 000516) = "0". (No wait for internal accessing) Not exceeding 16MHz if wait bit (bit 7 of address 000516) = "1". (1 wait for internal accessing) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU reprogram mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction (3) Interrupts inhibited against use _______ The NMI, address match and WDC interrupts cannot be used during CPU reprogram mode because they refer to the internal data of the flash memory. If interrupts have their vectors in the variable vector table, they can be used by transferring the vector into the RAM area. (4) Reset The reset is always receivable. (5) The reprogram in user ROM area When CPU reprogram mode is entered and the block that the flash reprogram control program is located is being reprogramming, the block may not be reprogrammed correctly if the power supply is suddenly down. It is possible that the flash reprogram cannot be executed again in this case. Thus, it is recommended to use standard serial I/O mode and parallel I/O mode.
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CPU Reprogram Mode
Software commands
Table BB-1 lists the S/W commands available. After setting the CPU reprogram mode select bit to "1", the S/W commands can be used to specify the erasing or programming operation. Note that when entering a S/W command, the upper byte (D15-D8) is ignored. The content of each S/W command is explained below. Table BB-1 List of software commands (CPU reprogram mode) The 1st bus cycle Cycle Command Data Mode Address number (D15-D0) Read array 1 Write X (Note 5) FF16 Read status register 2 Write X 7016 Clear status register 1 Write X 5016 Program 2 Write X 4016 Block erase 2 Write X 2016
The 2nd bus cycle Data Mode Address (D15-D0) Read Write Write X WA(Note 3) BA(Note 4) SRD(Note 2) WD(Note 3) D016
Note 1: When a S/W command is input, the high-order byte of the data(D15-D8) is ignored. Note 2: SRD = Status Register Data. The address should be even and within the user ROM area. Note 3: WA = Write Address, WD = Write Data Note 4: BA = Block Address (the maximum even address of the block) Note 5: "X" can be any even address in user ROM area.
Read Array Command (FF16) Issuing the command code "FF16" in the 1st bus cycle enters the read array mode. When an even address is issued in one of the bus cycle that follows, the content of the address is read out at the data bus (D15-D0), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code "7016" is issued in the 1st bus cycle, the content of the status register is read out at the data bus (D7-D0) by a read in the 2nd bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) The command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in error. To use this command, issue the command code "5016" in the 1st bus cycle.
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M16C/6K9 Group
CPU Reprogram Mode
Program Command (4016) Program operation starts when the command code "4016" is issued in the 1st bus cycle. If the address and data are issued in the 2nd bus cycle, program operation (data programming and verification) will start. _____ Whether the program operation is completed can be conformed by reading the status register or the RY/BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register can be read on the date bus (D7-D0). The status register bit 7 (SR7) is set to "0" at the same time when the program operation starts and is returned to "1" upon the completion of the program operation. In this case, the read status register mode remains active until the Read Array Command (FF16) is issued. _____ The RY/BY status flag is "0" during program operation and "1" when the program operation is completed same as the status register bit 7. After the program, reading the status register can check the result. Refer to the section where the status register is detailed.
Start
Write 4016
Write Write address Write data (The address for reading the status register should be even and within the user ROM area.)
Status register read
SR7=1? or RY/BY=1?
NO
YES NO
SR4=0?
Program error
YES Program completed
Fig.BB-3 Program flowchart
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M16C/6K9 Group
CPU Reprogram Mode
Block Erase Command (2016/D016) By issuing the command code "2016" in the 1st bus cycle and the conformation command code "D016" and block address in the 2nd bus cycle, the erase operation specified by the block address starts (erase and erase verification). _____ Whether the block erase command is terminated can be conformed by reading the status register or the RY/BY status flag. When the block erase operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time when the erase operation starts and is returned to "1" upon the completion of the erase operation. In this case, the read status register mode remains active until the Read Array Command (FF16) is written. _____ The RY/BY status flag is "0" during erase operation and "1" when the erase operation is completed the same as the bit 7 of status register. After the block erase, reading the status register can check the result. Refer to the section where the status register is detailed.
Start
Write 2016
Write D016 Block address (The address for reading the status register should be even and within the user ROM area.)
Status register read
SR7=1? or RY/BY=1?
NO
YES
Full status check (Note 1)
Error
Erase error
Erase completed
Note 1: Refer to Fig. BB-5.
Fig.BB-4 Erase flowchart
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CPU Reprogram Mode
Status register
The status register shows the operation status of the flash memory and whether program and erase operations end successfully or not. It can be read in the following conditions. (1) By reading an arbitrary address from the user ROM area after issuing the read status register command (7016) (2) By reading an arbitrary address from the user ROM area in the period from the start of program or erase operation to the execution of read array command (FF16). Table BB-2 shows the status register. The status register can be cleared in the following condition. (1) By issuing the clear status register command (5016). (2) After reset, the status register is set to "8016". Each bit of the register is shows below. Sequencer status (SR7) After power-on, the sequencer status is set to "1" (ready). The bit is set to "0" (busy) during program and erase operations and is set to "1" upon the completion of these operations. Erase status (SR5) Erase status indicates the status of erase operation. When erase error occurs, it is set to "1". The bit becomes "0" when it is cleared. Program status (SR4) Program status indicates the status of program operation. When program error occurs, it is set to "1". The bit becomes "0" when it is cleared. If "1" is set to SR5 or SR4, the program and block erase operations are not accepted. Before execution of these commands, it is necessary to execute the clear status register command (5016) to clear the status register. If any S/W commands are not correct, both the SR5 and SR4 are set to "1".
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CPU Reprogram Mode
Table BB-2 Definition of each bit of status register
Each bit of SRD SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Reserved
Status name Sequencer status Erase status Program status Reserved Reserved Reserved Reserved
Definition "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
Full status check By performing full status check, the execution result of erase and program operations can be known. Fig.BB-5 shows the full status check flowchart and the method to deal with the error.
Read status register
SR4=1 and SR5=1? NO SR5=0? YES SR4=0? YES
YES
Command sequence error
Execute the clear status register command (5016) to clear the status register. Try to perform the operation again after conforming that the command is entered correctly. Should block erase error occur, the block cannot be used.
NO
Block erase error
NO
Program error
Should program error occur, the block cannot be used.
End (block erase, program)
Note: When SR5 or SR4 is set to "1", neither of the program nor block erase commands are accepted. Execute the clear status register command (5016) before executing these commands.
Fig.BB-5 Full status check flowchart and the method to deal with errors
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M16C/6K9 Group
Functions To Inhibit Rewriting Flash Memory
Functions to inhibit rewriting to the on-chip flash memory
To prevent flash memory from being miss-read or miss-written, ROM code protect function for parallel I/O mode and ID code check function for standard serial mode are introduced. ROM code protect function ROM code protect function can inhibit readout from or modification to the flash memory by setting the content in ROM code protect control address (0FFFFF16) for parallel I/O mode. Fig.BB-6 shows the content of ROM code protect control address (0FFFFF16). (The address exists in user ROM area.) If one of the pair of ROM code protect bits is set to "0", ROM code protect is turned on, so that the flash memory is protected against the readout or modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When both level 1 and level 2 are set, level 2 will be selected. If both of the two ROM code protect reset bits are set to "00", ROM code protect is turned off, so that the flash memory can be read out or modified. Once ROM code protect is turned on, the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial mode or other to rewrite these two bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROMCP Bit symbol
Address
0FFFFF16
When reset
FF16
11
Bit name
Function Always set these bits to "1"
b3 b2
Reserved bits
ROMCP2 ROM code protect level 2 set bits (Note 1,2)
0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled
b5 b4
ROMCR
0 0: Protect removed ROM code protect reset 0 1: Protect set bits effective bits (Note 3) 1 0: Protect set bits effective 1 1: Protect set bits effective
b7 b6
0 0: Protect enabled ROMCP1 ROM code protect level 0 1: Protect enabled 1 0: Protect enabled 1 set bits (Note 1) 1 1: Protect disabled Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel I/O mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester,etc. is also inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and level 2. However,Since these bits can not be modified in parallel I/O mode, they should be rewritten in serial I/O mode or other modes.
Fig.BB-6 ROM code protect control address
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M16C/6K9 Group
Functions To Inhibit Rewriting Flash Memory
ID code check function
The function is used in standard serial I/O mode. If the flash memory is not blank, the ID code sent from serial burner is compared with that inside flash memory to check the agreement. It the ID codes do not match, the commands from serial burner are not accepted. Each ID code consists of 8-bit data, the areas of which, beginning from the 1 st byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, 0FFFFB16. Write a program with the ID code at these addresses to the flash memory.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID3 ID4 ID5 ID6 ID7 ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector Reset vector
4 bytes
Fig.BB-7 ROM ID code addresses
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M16C/6K9 Group
Parallel I/O Mode
Parallel I/O mode
Parallel I/O mode is to input and output the software command, address and data in parallel to access the on-chip flash memory (read, program, erase etc.). Please use the specific device (programmer) supported for M16C/6K9 Group. Referring to the guideline etc. of each device manufacture for the usage.
User ROM area and boot ROM area
In parallel I/O mode, both user ROM area and boot ROM area showed in Fig.AB-1 can be reprogrammed. The access method to both areas is the same. The size of boot ROM area is 4K bytes. The addresses are allocated in 0FF00016- 0FFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, erase block operation is applied to only one 4K bytes block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from Renesas factory. Therefore, if the standard serial I/O mode is used, the rewriting to the boot ROM area is not necessary.
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M16C/6K9 Group
Standard Serial I/O Mode
Table EE-1 Pin function (Flash memory standard serial I/O mode) Pin name Name I/O VCC, VSS Power supply Apply 3.3 0.3V to VCC, apply 0V to VSS M0 M0 I Connect to VCC ____________ RESET Reset input I Reset input pin. While reset is "L", 20 cycles or more clocks input to XIN pin are needed. XIN Clock input I Connect a ceramic resonator or crystal oscillator XOUT Clock output O between XIN and XOUT. If external clock is used, input it to XIN pin and open the XOUT pin. M1 M1 I Connect to VSS FVCC Power supply input Apply 3.0V to 3.6V for flash program AVCC, AVSS Analog power supply Connect AVSS to VSS, AVCC to VCC VREF Reference voltage I The input pin of reference voltage of AD converter P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P63 P64 P65 P66 P67 P70-P77 P80-P84 P86,P87 P85 P90-P97 P100-P107 P110-P117 P120-P127 P130-P137 P140-P147 P150-P157 P160,P161 Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 Input port P6 BUSY output SCLK input RXD input TXD input Input port P7 Input port P8
______
I I I I I I I O I I O I I I I I I I I I I I
Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open The output pin of BUSY signal The input pin of serial clock The input pin if serial data The output pin of serial data Input "H", "L" or open Input "H", "L" or open Connect to VCC The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data
NMI input Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Input port P14 Input port P15 Input port P16
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Standard Serial I/O Mode
108 107 106 105 104 103 102 101 100 99
84 83
98 97 96 95 94 93 92 91 90 89 88 87 86 85
82 81 80
P10/CTS01/RTS01 P126 P125/INT111 P124/INT102 P123/INT92 P122/INT82 P121/INT72 P120/INT61 P07 P06 P05 P04 P03 P02 P01 P00 P117 P116 P115 P114 P113 P112 P111/F1OUT1 P110/F1OUT0 P107/AN7/INT110 P106/AN6/INT100 P105/AN5/INT90 P104/AN4/INT80 P103/AN3/INT70 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN40/INT60
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 25 1 26 1 27 1 128 129 130 131 132 133 134 135 136 137 138 139 40 1 41 1 42 1 143 144 1 2345 678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
79 78 77 76 75 74 73
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P11/CLK01 P12/RXD01 P13/TXD01 P14/INT71/CTS11/RTS11/CTS01/CLKS11 P15/INT81/CLK11 P16/INT91/RXD11 P17/INT101/TXD11 P20/TXD21 P21/RXD21 P22/CLK21 P23/CTS21/RTS21 P24 P25 P26 P27 VSS P30/LAD0 VCC P127 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37 P130 P131 P132 P133 P134 P135 P136 P137 P40/ TA00OUT/OBF00/PWM41 P41/TA10OUT/PWM51
M306K9FCLRP M306K9F8LRP (144PFB)
P42/TA20OUT/GATEA20 P43/OBF01 P44/PWM01/OBF1 P45/PWM11/OBF2 P46/PWM21/OBF3 FVCC P47/PWM31 VSS P140/KI10 P141/KI11 P142/KI12 P143/KI13 P144/KI14 P145/KI15 P146/KI16 P147/KI17 P50/KI00 P51/KI01 P52/KI02 P53/KI03 P54/KI04 P55/KI05 P56/KI06 P57 /CLKOUT/KI07 P150/TA01OUT P151/TA11OUT P152/TA21OUT P60/CTS00/RTS00/SDA0 P61/CLK00/SCL0 P62/RXD00/SDA1 P63/TXD00/SCL1 P64/CTS10/RTS10 /CTS00/CLKS10 P65/CLK10 P66/RXD10/TA3OUT P67/TXD10/TA4OUT P70/TXD20/PS2A0
FVCC
BUSY RXD
SCLK TXD
P92/SOUT30/INT5 P91/SIN30/INT4 P90/CLK30/INT3 P161/TB41IN/PWM50 P160/TB31IN/PWM40 P157/SIN41 P156/SOUT41 P155/CLK41 P154 P153 M1 M0 P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/TB2IN P83/TB1IN P82/TB0IN P81/TA4IN P80/ICCK P77/TA3IN/SCL2 P76/SDA2 P75/TA2IN/INT2/PS2B2 P74/INT1/PS2B1 P73/CTS20/RTS20/TA1IN/INT0/PS2B0 P72/CLK20/PS2A2 P71/RXD20/TA0IN/TB5IN/PS2A1
P96/ANEX1/SOUT40/PWM30 P95/ANEX0/CLK40/PWM20 P94/DA1/TB40IN/PWM10 P93/DA0/TB30IN/PWM00
VSS VCC
RESET
Connect to oscillation circuit
Mode setting method Name of signal line Value M0 M1 FVCC RESET VCC VSS 3.0V to 3.6V VSS VCC
Fig.EE-1 Pin connections for serial I/O mode
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M1 M0
M16C/6K9 Group
Standard Serial I/O Mode
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the S/W commands, addresses and data needed to operate (read, program, erase etc.) the on-chip flash memory with a dedicated serial programmer. Different from parallel I/O mode, in standard serial mode, CPU controls the flash memory reprogramming (uses the CPU reprogram mode) and the input of serial reprogram data etc. The standard serial I/O mode is started by connecting M0 to "H", M1 to "L" and applying 3.0V to 3.6V externally to FVCC with the release of reset. (To connect M0 to "L" in normal microcomputer mode.) This control program is written in boot ROM area when the product is shipped from Renesas factory. Make sure that the standard serial I/O mode cannot be used if boot ROM area is written in parallel I/O mode. Fig EE-1 shows the pin connections for standard serial I/O mode. The input and output of serial data are processed in CLK10, RxD10, TxD10, RTS10 (BUSY) 4 pins of the UART1. The CLK10 is clock input pin, which clock is input externally. The TxD10 is CMOS output pin. The RTS10 (BUSY) pin outputs "L" when ready for reception and outputs "H" when reception starts. The serial data are transferred in 8-bit unit. In standard serial I/O mode, only the user ROM area shown in Fig.AB-1 can be reprogrammed. Boot ROM area cannot be reprogrammed. In the standard serial I/O mode, a 7-byte ID code is used. If the flash memory is not blank, commands sent from programmer are not accepted unless the ID code matches.
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Standard Serial I/O Mode
Outline (standard serial I/O mode)
In standard serial I/O mode, S/W commands, addresses, and data etc. are input and output with the peripheral device (serial programmer) using 4-wire clock-synchronized serial I/O (UART1). In reception, S/W commands, addresses and program data are read from RxD10 pin synchronized with the rising edge of the transfer clock that is input to the CLK10 pin. In transmission, the read data and status are output to TxD10 pin synchronized with the falling edge of the transfer clock. The TxD10 is CMOS output pin. Transfer is in 8-bit unit with LSB first. During transmission, reception, erasing and programming, the RTS10 (BUSY) pin is "H". Accordingly, always start the next transfer after the RTS10 (BUSY) pin becomes "L". The read after the input of S/W commands can get memory data and status register. Reading the status register can check the flash memory operation status, the normal/error end of erasing or programming operation. The following are the explanation of S/W commands, status register etc.
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M16C/6K9 Group
Standard Serial I/O Mode
S/W commands
Table EE-2 lists the S/W commands. In standard serial I/O mode, the S/W commands, which transferred from RxD pin, control of erase, program and read etc. The S/W commands in standard serial I/O mode are similar with that in parallel I/O mode. ID check function, download function, version information output function, boot ROM area output function and read check data, 5 commands are added. Table EE-2 The list of S/W commands (standard serial I/O mode)
Control 1 2 3 4 5 6 7 8 9 command Page read Page program Block erase Read status register Clear status register ID check function Download function Version information output function Boot ROM area 1st byte transfer FF16 4116 2016 7016 5016 F516 FA16 FB16 FC16 FD16 Address (low) Address (low) Version data output Address (middle) Check data (low) Address (middle) Address (high) Version data output Address (high) Check data (high) Address (high) Check sum Version ID size Data input Version ID1 No. of -ID7 -ID7 2nd byte Address (middle) Address (middle) Address (middle) SRD output 3rd byte Address (high) Address (high) Address (high) SRD1 output Not acceptable Acceptable Not acceptable Acceptable Not acceptable Not acceptable 4th byte Data output Data input D016 5th byte Data output Data input 6th byte Data output Data input - 259th byte data output 259th byte data input Not acceptable Acceptable If ID unmatched Not acceptable Not acceptable
times required Version -9th byte data output Data output Version data output -259th byte data output
data output data output Data Data output output
output function 10 Read check data
Note 1: Shading indicates transfer from flash memory on chip microcomputer to serial programmer. The else indicates transfer from serial programmer to flash memory on chip microcomputer. Note 2: SRD means status register data. SRD1 means status register 1 data. Note 3: All commands are acceptable if the flash memory is blank.
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M16C/6K9 Group
Standard Serial I/O Mode
The following are the descriptions of S/W commands
Page read command The command reads the specified page (256 bytes) of the flash memory sequentially one byte at a time. Execute the page read command as following: (1) Transfer the "FF16" command code in the 1st byte. (2) Transfer addresses A8- A15 and A16- A23 in the 2nd and 3rd byte respectively. (3) From the 4th byte onward, data (D7-D0) of the page specified by the address (A23-A8) will be output sequentially from the smallest address sync with the falling edge of the clock.
CLK10 A16 to A23
RxD10
(M16C reception data)
FF16
A8 to A15
TxD10
(M16C transmit data)
Data0
Data255
RTS10(BUSY)
Fig.EE-2 Timing of page read Read status register command The command is for reading status information. When command code "7016" is sent in the 1st byte, the contents of status register (SRD) and status register 1 (SRD1) will be output in the 2nd and 3rd byte respectively sync with the falling edge of the clock.
CLK10
RxD10
(M16C reception data)
7016
TxD10
(M16C transmit data)
SRD output
SRD1 output
RTS10(BUSY)
Fig.EE-3 Timing of read status register
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M16C/6K9 Group
Standard Serial I/O Mode
Clear status register command The command clears the bits (SR4-SR5), which are set when operation ended in error. When command code "5016" is sent in the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS10 (BUSY) signal changes from "H" to "L".
CLK10
RxD10
(M16C reception data)
5016
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-4 Timing of clear status register Page program command The command programs the specified page (256 bytes) of flash memory sequentially one byte a time. Execute the command as follows: (1) Transfer the command code "4116" in the 1st byte. (2) Transfer addresses A15-A8 and A23-A16 in the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, after inputting 256 bytes program data (A7-A0) from the smallest address of the specified page, the page program operation will be executed automatically. When the reception for the next 256 bytes is setup, the RTS10 (BUSY) signal changes from "H" to "L". The result of the page program can be known by reading the status register. For more detail, see the section on the status register.
CLK10
RxD10
(M16C reception data)
4116
A8 to A15
A16 to A23
Data0
Data255
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-5 Timing of page program
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M16C/6K9 Group
Standard Serial I/O Mode
Block erase command The command erases the data in the specified block. Execute the command as follows: (1) Transfer the command code "2016" in the 1st byte. (2) Transfer addresses A15-A8 and A23-A16 in the 2nd and 3rd bytes respectively. (3) After transferring the verify command code"D016" in the 4th byte, the erase operation starts for the specified block of the flash memory. Issue the biggest address of th2e specified block to A23-A8. After the completion of block erase, the RTS10 (BUSY) signal changes from "H" to "L". The result of the block erase can be know by reading the status register. For more detail, see the section on the status register.
CLK10
RxD10
(M16C reception data)
2016
A8 to A15
A16 to A23
D016
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-6 Timing of block erase
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M16C/6K9 Group
Standard Serial I/O Mode
Download function The command downloads an execution program to RAM. Execute the command as follows: (1) Transfer the command code "FA16" in the 1st byte. (2) Transfer the program size in the 2nd and 3rd bytes. (3) Transfer the checksum in the 4th byte. Check sum is calculated from all transferred data from the 5th byte onward. (4) The execution program is transferred from 5th byte onward. After the entire program data have been transferred, the downloaded execution program will be executed if the checksum matches. The program size allowed to transfer varies according to the size of on-chip RAM.
CLK10
RxD10
(M16C reception data)
FA16
Data size Data size
(low)
(high)
Check sum
Program data
Program data
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-7 Timing of download function
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M16C/6K9 Group
Standard Serial I/O Mode
Version information output function The version information of the control program stored in boot ROM area can be output by the function. Execute the command as follows: (1) Transfer the command code "FB16" in the 1st byte. (2) From the 2nd byte onward, the version information will be output. The information is composed of 8 ASCII character code.
CLK10
RxD10
(M16C reception data)
FB16
TxD10
(M16C transmit data)
'V'
'E'
'R'
'X'
RTS10(BUSY)
Fig.EE-8 Timing of version information output function
Boot ROM area output function The control program stored in boot ROM area can be read out in page (256 bytes) unit by the function. Execute the command as follows: (1) Transfer the command code "FC16" in the 1st byte. (2) Transfer addresses A15-A8 and A23-A16 in the 2nd and 3rd bytes respectively. From the 4th byte onward, the data (D7-D0) specified in page (256 bytes) address A23-A8 will be output sequentially from the smallest address in sync with the rising edge of the clock.
CLK10
RxD10
(M16C reception data)
FC16
A8 to A15
A16 to A23
TxD10
(M16C transmit data)
Data0
Data255
RTS10(BUSY)
Fig.EE-9 Timing og boot ROM area output function
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M16C/6K9 Group
Standard Serial I/O Mode
ID check function The command checks the ID code. Execute the command as follows: (1) Transfer the command code "F516" in the 1st byte. (2) Transfer addresses A7-A0, A15-A8 and A23-A16 of 1st ID code (ID1) in the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of the ID code in the 5th byte. (4) From the 6th byte onward, transfer the IDs from the 1st ID code (ID1).
CLK10
RxD10
(M16C reception data)
F516
DF16
FF16
0F16
IDsize
ID1
ID7
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-10 Timing of ID check function ID code If the flash memory is not blank, the input ID codes are compared with that written in flash memory. If they do not match, the input commands will not be accepted. Each ID code contains 8 bits data. Beginning from the 1st ID byte, the address of each ID code is 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16 respectively. Write the program with the ID codes in these addresses to the flash memory.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID3 ID4 ID5 ID6 ID7 ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector Reset vector
4 bytes
Fig.EE-11 ID code addressed
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M16C/6K9 Group
Standard Serial I/O Mode
Read check data Read check date command is for conforming if the reprogram data sent after page program command have been received correctly. (1) Transfer the command code "FD16" in the 1st byte. (2) Transfer check data (low) and check data (high) in the 2nd and 3rd bytes respectively. When using read check data command, the command should be issued at first to initialize the check data. The next is to issue the page program command and related reprogram data. After that, by issuing the read check data command again, the check data for the reprogram data issued between the two read check data command can be read out. Adding the reprogram data in byte unit and then calculating the lower 2 bytes of the added data in two's complement gives out the check data.
CLK10
RxD10
(M16C reception data)
FD16
TxD10
(M16C transmit data)
Check data (low)
Check data (high)
RTS10(BUSY)
Fig.EE-12 Timing of read check dt command
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M16C/6K9 Group
Standard Serial I/O Mode
Status register Status register indicates if the operation to the flash memory ends successfully or in error. It can be read by issuing the read status register command (7016). The status register can be cleared by issuing the clear status register command (5016). Table EE-3 shows the definition of each bit of the register. After reset, status register outputs "8016".
Table EE-3 Status register (SRD)
Definition Symbol SR7 (D7) SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) SR0 (D0) Status Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
Sequencer status (SR7) After power-on, the sequencer status is set to "1" (ready). The bit is set to "0" (busy) during program and erase operations and is set to "1" upon the completion of these operations. Erase status (SR5) Erase status indicates the status of erase operation. When erase error occurs, it is set to "1". The bit becomes "0" when it is cleared. Program status (SR4) Program status indicates the status of program operation. When program error occurs, it is set to "1". The bit becomes "0" when it is cleared.
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M16C/6K9 Group
Standard Serial I/O Mode
Status register 1 (SRD1) Status register 1 indicates the status of serial communication, the result of ID codes comparison, the result of checksum comparison etc. It can be read after SDR by issuing the read status register command (7016). The register can be cleared by issuing the clear status register command (5016). Table EE-4 shows the definition of each bit of the register. After power on, status register 1 outputs "0016".
Table EE-4 Status register (SRD1)
Each bit of SRD SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2)
Definition Status name Boot update completed bit Reserved Reserved Check sum match bit ID check completed bits Match 00 01 10 11 "1" Update completed Mismatch Not verified Verified with mismatch Reserved Verified with match Normal operation "0" Not update -
SR9 (bit1) SR8 (bit0)
Timeout of data reception Reserved
Timeout
Boot update completed bit (SR15) The flag indicates that if the control program has been downloaded to RAM with download function. Check sum match bit (SR12) The flag indicates if the check sum is matched when downloading the control program with download function. ID check completed bits (SR11, SR10) These bits indicate the result of ID checks. Some commands cannot be accepted without the ID checks. Timeout of data reception bit (SR9) The flag indicates if timeout occurs during data reception. If the bit is set to "1" during data reception, microcomputer will discard the received data and return to wait state.
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M16C/6K9 Group
Standard Serial I/O Mode
Full status check
By performing full status check, the execution result of erase and program operations can be known. Fig.EE13 shows the full status check flowchart and the method to deal with the error.
Read status register
SR4=1 ? and YES SR5=1 ? NO SR5=0? YES SR4=0? YES NO NO
Command sequence error
Execute the clear status register command (5016) to clear the status register. Try to perform the operation again after conforming that the commands is entered correctly. Should block erase error occur, the block can not be used.
Block erase error
Program error
Should program error occur, the block can not be used.
End (block erase, program)
Note: When SR5 or SR4 is set to "1", neither of the program nor block erase commands are accepted. Execute the clear status register command (5016) before executing these commands.
Fig.EE-13 Full status check flowchart and the method to deal with errors
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M16C/6K9 Group
Standard Serial I/O Mode
Circuit applied for standard serial I/O mode (example)
The figure below shows a circuit applied for standard serial I/O mode. The control pins bary by different programmer. Refer to programmer manual for the detail.
Clock input BUSY output Data input Clock output
CLK10 RTS10(BUSY) RXD10 TXD10 M16C/6K9 (NEW DINOR type flash memory) M0 M1 NMI
The control pins and external circuitry vary by different programmer. Refer to programmer manual for the detail.
Fig.EE-14 Example circuit applied for the standard serial I/O mode
Rev.1.00
Jun 06, 2003
page 289 of 290
M16C/6K9 Group
Package
Package
144PFB-A
MMP
JEDEC Code - Weight(g) 0.62 Lead Material Cu Alloy
Plastic 144pin 16 16mm body TQFP
MD
e
EIAJ Package Code TQFP144-P-1616-0.40
HD D
144 1 109 108
b2
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
A3
36 37 72
73
A L1
e
F
A2
x y b2 I2 MD ME
y
b
x
L Detail F Lp
M
Dimension in Millimeters Min Nom Max - - 1.2 0.05 0.1 0.15 1.0 - - 0.13 0.18 0.23 0.105 0.125 0.175 15.9 16.0 16.1 15.9 16.0 16.1 0.4 - - 17.8 18.0 18.2 17.8 18.0 18.2 0.4 0.5 0.6 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.07 0.08 - - 0 8 - 0.225 - - 1.0 - - - 16.4 - - 16.4 -
HE
E
A1
Rev.1.00
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page 290 of 290
c
ME
REVISION HISTORY
Rev. Date Page 1.00 Jun. 6, 2003 - First edition issued
M16C/6K9 Group Data Sheet
Description Summary
(1/1)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
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